Hi,
My customer is using C6657, they have problem with PCIe communication.
The DSP uses PCIe boot, PC side as a Root Complex and DSP side as a Endpoint.
The problem is that when loading a DSP image from RC into DSP internal memory(MSMC RAM), sometimes data is not loaded correctly.
The customer performed the method suggested in the following thread.
e2e.ti.com/.../279249
> you can try to write to IB_OFFSET first and then add Read-back of this register, before you start the data stream writing.
==> The problem was solved by executing the above method.
> You can try to locate the Relaxed Ordering related register in RC (such as TLP Configuration register, Device Control register) to disable this feature.
==> However, the above method did not solve the problem.
So we have the following questions.
Q1: The customer disabled the Relaxed Ordering function, but the problem was not solved. What do you know the reason for this?
Q2: Is it necessary to wait for a certain amount of time after mapping is completed with inbound offset processing?
Is this also a requirement specification of DSP?
Best regards,
H.U
