66AK2E05: SGMII CLOCK PLL registers ?

Hi,

We're looking into this. Feedback will be posted here.

Best Regards,
Yordan

Hello,
I want to clarify that, In K2E EVM the SGMII Reference clock is 156.25MHz but our custom board has 125MHz clock.
will you let me know, is there any register setting are required?
As Ethernet is not working on our board so i have a doubt that due to change in reference clock, it is not working.
PHY to PC link is up but K2E MAC SGMII to PHY link is not up.
so, please let me know, what are the K2E registers are required to change for 125MHz SGMII Clock as i am not able to find with the given K2E Datasheet and K2E GbE user guide.

Thanks and Regards
Tarang Jindal

Hi,

You can look into the
pdk_k2e_4_0_x\packages\ti\drv\pa\example\emacExample\src\c66x\bios\cpsw_mgmt.c. Init_SGMII_SERDES()

For K2E EVM,
serdes_lane_enable_params1.ref_clock = CSL_SERDES_REF_CLOCK_156p25M;

It calls into CSL function:
static inline CSL_SERDES_RESULT CSL_EthernetSerdesInit
(
uint32_t base_addr,
CSL_SERDES_REF_CLOCK ref_clock,
CSL_SERDES_LINK_RATE rate
)

else if (ref_clock == CSL_SERDES_REF_CLOCK_156p25M && rate == CSL_SERDES_LINK_RATE_1p25G)
{
csl_wiz8_sb_refclk156p25MHz_10bit_5Gbps(base_addr);
}

For your case, if you use the 125MHz reference clock,

if (ref_clock == CSL_SERDES_REF_CLOCK_125M && rate == CSL_SERDES_LINK_RATE_1p25G)
{
csl_wiz8_sb_refclk125MHz_10bit_5Gbps(base_addr);
}

So, your function needs calling into csl_wiz8_sb_refclk125MHz_10bit_5Gbps() to setup PLL and serdes.

Regards, Eric

Hi Eric, 

There is some misunderstanding, the issue ( SGMII CLOCK PLL register ?)  we are facing on u-boot. 

Regards,

Arun 

Hello Sir,
We are working on uboot. but there is no link between K2E SGMII to DPE83867 PHY.
We are using the K2E EVM uboot as reference but in K2E EVM the SGMII ref clock is 156.25MHz and our board has 125MHz.

so, please tell us that which registers of K2E devices are related to SGMII Clock PLL settings?
also, what changes are required in uBoot code for the same.

Thanks and regards
Tarang Jindal

Hi,

I asked our Linux team to comment.

Regards, Eric

Hello, 

We have changed the "SERDES_CLOCK_156P25M" from "SERDES_CLOCK_125M" in keystone_net.c. 

but it is also not helping. We are still not able to get the link between SoC SGMII port-0 and DPE83867 PHY.

will you assure us that the SoC SGMII will work on 125MHz SGMII reference clock? 

Also if 125MHz clock is acceptable then what are the changes we need to done at uBoot other than keystone_net.c. file. 

Thanks and Regards

Tarang Jindal

Hi, Tarang,

The SerDes spec indicates both frequencies are supported.

Rex