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Compiler/TMS320C6678: TMS320C6678 Download file error

Part Number: TMS320C6678

Tool/software: TI C/C++ Compiler

When i using CCS through XDS560v2 to rdownload a simple porject  such as helloworld

I get the following message:

C66xx_0: GEL Output: Setup_Memory_Map...
C66xx_0: GEL Output: Setup_Memory_Map... Done.
C66xx_0: GEL Output:
Connecting Target...
C66xx_0: GEL Output: DSP core #0
C66xx_0: GEL Output: C6678L GEL file Ver is 2.0
C66xx_0: GEL Output: Global Default Setup...
C66xx_0: GEL Output: Setup Cache...
C66xx_0: GEL Output: L1P = 32K  
C66xx_0: GEL Output: L1D = 32K  
C66xx_0: GEL Output: L2 = ALL SRAM  
C66xx_0: GEL Output: Setup Cache... Done.
C66xx_0: GEL Output: Main PLL (PLL1) Setup ...
C66xx_0: GEL Output: PLL in Bypass ...
C66xx_0: GEL Output: PLL1 Setup for DSP @ 1000.0 MHz.
C66xx_0: GEL Output:            SYSCLK2 = 333.3333 MHz, SYSCLK5 = 200.0 MHz.
C66xx_0: GEL Output:            SYSCLK8 = 15.625 MHz.
C66xx_0: GEL Output: PLL1 Setup... Done.
C66xx_0: GEL Output: DSP core #64 cannot set PSC.
C66xx_0: GEL Output: PA PLL (PLL3) Setup ...
C66xx_0: GEL Output: DSP core #64 cannot set PA PLL
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ...
C66xx_0: GEL Output: DSP core #64 cannot set DDR3 PLL
C66xx_0: GEL Output: DDR begin (1333 auto)
C66xx_0: GEL Output: XMC Setup ... Done
C66xx_0: GEL Output:
DDR3 initialization is complete.
C66xx_0: GEL Output: DDR done
C66xx_0: GEL Output: DDR3 memory test... Started
C66xx_0: GEL Output: DDR3 memory test... Failed
C66xx_0: GEL Output: Main PLL (PLL1) Setup ...
C66xx_0: GEL Output: DSP core #64 cannot set PLL1.
C66xx_0: GEL Output: Error in Setting up main PLL, please power cycle the board and re-run Global Default Setup

I have five  pieces of boards ,the other four are all ok 。I have measure the power ,input  clock (100M Hz) ,reset  signal, It turns out to be normal .and the sysclkout  is 16.6M Hz .

Where is the problem?

Thank you very much

                   

  • Can you verify the power-up sequence complies with the data manual recommendations?
    7.3.1 Power-Supply Sequencing
    This section defines the requirements for a power up sequencing from a power-on reset condition. There are two acceptable power sequences for the device. The first sequence stipulates the core voltages starting before the IO voltages as shown below.
    1. CVDD
    2. CVDD1, VDDT1-2
    3. DVDD18, AVDD1, AVDD2
    4. DVDD15, VDDR1-4
    The second sequence provides compatibility with other TI processors with the IO voltage starting before the core voltages as shown below.
    1. DVDD18, AVDD1, AVDD2
    2. CVDD
    3. CVDD1, VDDT1-2
    4. DVDD15, VDDR1-4

    Best Regards,
    Yordan
  • Yordan

                The Power-Supply Sequence complies with  the data manual recommendations and the core voltage starts before the IO voltage .

    I have five pieces of boards and only one have the error .

    Best Regards,

    Zhen

  • Hi Zhen,

    I have five pieces of boards and only one have the error .


    This is exactly what got me thinking that this is a hw issue. Are you able to access main PLL without loading the gel file (through the memory browser of CCS)?

    Best Regards,
    Yordan
  • Yordan,

                  I have no idea on accessing  main PLL without loading the gel file through the memory browser of ccs .

    Can you give me some relevant documents?

    Best Regards,

    zhen

  • Hi,

    In general this can be done through the memory browser. You can enter the address of the register & see its value or set it. However, this may not be a good idea.
    You say:

    I have measure the power ,input clock (100M Hz) ,reset signal, It turns out to be normal .and the sysclkout is 16.6M Hz .

    Did your input clock have a lot of jitter (is it stable)? Are you working at the maximum/minimum ratings on some power supply (or timing)? Did you review your PCB?

    It is not logical to have the same software running on 4 boards & failing on the fifth and think that this is a problem with the software. As far as I see your ddr test failed as well:
    C66xx_0: GEL Output: DDR3 memory test... Failed

    If you still want to debug the gel file, what you can do is add debug prints in the gel file on each step (register setting) and see where exactly it is failing (during which register access) and come back with the results.

    Best Regards,
    Yordan

  • Yordan.

    i have  trouble in downloading  file without GEL file,and connect the dsp.iIam a hw engineer.I want to know how to do it.and i want to know the error that the main pll cannot be set does mean.

    Best regards

    Yang

  • If you open the gel file, located in , you will see that your error comes from here:
    if (DNUM == 0)
    {
    for (count = 0; count < PLL_REINIT_MAX_COUNT; count++) {
    // Setup Pll1 DSP @ TARGET_FREQ
    status = Init_PLL(PLL1_M, PLL1_D);

    if (status == -1) {
    GEL_TextOut( "Error in Setting up main PLL, please power cycle the board and re-run Global Default Setup...\n" );
    while (1);
    }
    Specifically from the line status = Init_PLL(PLL1_M, PLL1_D);.

    This means that the code cannot program PLL1_M & PLL1_D into the registers, this is done in Init_PLL():
    init_pll

    Digging deeper into the code you will see that the actual function that programs the multipliers & dividers is prog_pll1_values():
    prog_pll1_values(unsigned int pll_multiplier, unsigned int pll_divider, unsigned int odiv)
    {
    int TEMP;

    /* Check the Range for the parameters */

    if (odiv > 15)
    {
    GEL_TextOut ( " invalid output divide range, should be less than 15... \n");
    }

    if (pll_multiplier > 4095)
    {
    GEL_TextOut ( " invalid pll multiplier range, should be less than 4095... \n");
    }

    if (pll_divider > 63)
    {
    GEL_TextOut ( " invalid pll multiplier range, should be less than 63... \n");
    }

    /* Set the PLL Multiplier, Divider, BWADJ *
    * The PLLM[5:0] bits of the multiplier are controlled by the PLLM Register *
    * inside the PLL Controller and the PLLM[12:6] bits are controlled by the *
    * chip-level MAINPLLCTL0 Register. *
    * PLL Control Register (PLLM) Layout *
    * |31...6 |5...0 | *
    * |Reserved |PLLM | *
    * *
    * Main PLL Control Register (MAINPLLCTL0) *
    * |31...24 |23...19 |18...12 | 11...6 |5...0 | *
    * |BWADJ[7:0]| Reserved |PLLM[12:6] | Reserved | PLLD | */

    /* Set pll multipler (13 bit field) */
    PLL1_PLLM = (pll_multiplier & 0x0000003F); /* bits[5:0] */
    TEMP = (pll_multiplier & 0x1FC0) >> 6;/* bits[12:6] */
    MAINPLLCTL0 &=~(0x0007F000); /*Clear PLLM field */
    MAINPLLCTL0 |=((TEMP << 12) & 0x0007F000);

    /* Set the BWADJ (12 bit field) *
    * BWADJ[11:8] and BWADJ[7:0] are located in MAINPLLCTL0 and MAINPLLCTL1 *
    * registers. BWADJ[11:0] should be programmed to a value equal to half of *
    * PLLM[12:0] value (round down if PLLM has an odd value) *
    * Example: If PLLM = 15, then BWADJ = 7 */
    TEMP = ((pll_multiplier + 1) >> 1) - 1; /* Divide the pllm by 2 */
    MAINPLLCTL0 &=~(0xFF000000); /* Clear the BWADJ Field */
    MAINPLLCTL0 |= ((TEMP << 24) & 0xFF000000);
    MAINPLLCTL1 &=~(0x0000000F); /* Clear the BWADJ field */
    MAINPLLCTL1 |= ((TEMP >> 8) & 0x0000000F);

    /* Set the pll divider (6 bit field) *
    * PLLD[5:0] is located in MAINPLLCTL0 */
    MAINPLLCTL0 &= ~(0x0000003F); /* Clear the Field */
    MAINPLLCTL0 |= (pll_divider & 0x0000003F);

    /* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */
    PLL1_SECCTL &= ~(0x00780000); /* Clear the field */
    PLL1_SECCTL |= ((odiv << 19) & 0x00780000) ;

    }
    So, you can add debug prints, using GEL_TextOut("debug print content"); on each step of the above function.

    Also there is quite good explanation how to set the PLL multipliers and dividers in the comments at the beginning of the GEL file:
    / The System PLL governs the device (CorePac) operating speed.
    //
    // Each board designer defines the CLKIN frequency. On the
    // TMDXEVM6678L,LE,LXE EVMs, the CLKIN frequency defined to 100MHz. The
    // values for PLL1_M(39) and PLL1_D(1) defined below are pre-set
    // to provide a 1000MHz operating frequency on the EVMs.
    //
    // Other board designs using different CLKIN frequencies and/or
    // applications that requiring other operating frequecies, the PLL can
    // be configured by adjusting PLL1_M and PLL1_D per the
    // following formula:
    //
    // Target Frequency (MHz) =
    // input_clock (MHz) * [(PLL1_M + 1)]/ (2 * (PLL1_D + 1) )
    //
    // Table 2-13, "C66x DSP System PLL Configuration" in the device data sheet,
    // focus.ti.com/.../tms320c6678.pdf provides the suggested
    // values for PLL1_M and PLL1_D for various input clocks and desired
    // operating frequencies.
    //
    // Please note that there might be multiple PLL1_M and PLL1_D
    // values for the same Input clock and Desired Device Speed as long as the
    // multipliers and dividers are in the acceptable range.
    //
    // More details on the PLL including the limitations on acceptable ranges
    // for multipliers and dividers are in the PLL's user guide at
    // http://www.ti.com/lit/sprugv2
    //
    // The table provides some sample values of PLL1_M and PLL1_D:
    //
    // Please select PLL1_M values such that 0 < PLL1_M <= 64
    // +--------------------+---------------+--------+--------+
    // | (CLK)Desired | (CLKIN) Input | | |
    // | Device Speed (MHz) | Clock (MHz) | PLL1_M | PLL1_D |
    // +--------------------+---------------+--------+--------+
    // | 1000 | 100 | 19 | 0 |
    // | 1000 | 100 (EVM) | 39 | 1 |
    // | 1250 | 100 | 24 | 0 |
    // | 1000 | 50 | 39 | 1 |
    // | 1000 | 156.25 | 63 | 4 |
    // +--------------------+---------------+--------+--------+
    //
    // +--------------------+---------------+--------+--------+
    // | PA PLL VCO | (CLKIN) Input | | |
    // | Rate (MHz) | Clock (MHz) | PLL1_M | PLL1_D |
    // +--------------------+---------------+--------+--------+
    // | 1050 | 100.00 (EVM) | 20 | 0 |
    // | 1044 | 122.88 | 31 | 1 |
    // | 1050 | 122.88 | 204 | 11 |
    // | 1050 | 156.25 | 335 | 24 |
    // +--------------------+---------------+--------+--------+
    //
    // +--------------------+---------------+--------+--------+
    // | DDR3 PLL VCO | (CLKIN) Input | | |
    // | Rate (MHz) | Clock (MHz) | PLL1_M | PLL1_D |
    // +--------------------+---------------+--------+--------+
    // | 1333 | 66.667 (EVM) | 19 | 0 |
    // | 1066 | 66.667 | 31 | 1 |
    // | 800 | 66.667 | 11 | 0 |
    // +--------------------+---------------+--------+--------+

    Try different PLL1_M & PLL1_D values to see if this is a problem with your device being able to achieve the currently set frequency.

    Best Regards,
    Yordan