• Resolved

66ak2l06: 66ak2l06 k2l evm

Part Number: 66ak2l06

Hello, we are trying to use the K2L EVM board (document ## 16_00176_03, Rev 3.03, June 15 2017) with a JESD interface.  The schematics show on sheet 10 of 47  the connector pin out for the FMC1 with signals JESD1_TXP_FMC1 AND JEST1_TXN_FMC1 on pins A22 and A23.  It also shows the JESD2_TXP_FMC1 AND JESD2_TXN_FMC1 on pins A26 and A27.  The schematics has a big red circle around these pairs.  Is this because these pairs are called out incorrectly in the table inserted in the schematic on sheet 12 of 47?  Our interface board is utilizing the JESD ports according to the schematic:

lamar process balls AG19/AG18 (schematic signal names JESD1/AIF0_TXP_SOC,  JESD1/AIF0_TXN_SOC) drive the JESD switch (U32) at pins 15/16 (schematic signal names JESD1_TXP_FMC1, JESD1_TXN_FMC1) which are then ac coupled to the FMC1 connector pins A22/A23.

is this correct?

Also, since the JESD switch is used, what do I need to do to set up the Xilinx which generates the multiplexing control on the switch accommodate my JESD lane arrangement on our board with both a DAC and ADC:

Our hardware JESD lane setup for our protoboard connected to the EVM:

For our DAC: (Using JESD subclass1, with 122.88MHZ CLOCK with 120KHZ sys ref as generated from EVM)

66AK2L06 transmit output [SHARED_SERDES_0]  JESD channel 0 differential pins AH18/AH17 => ROUTE TO => FMC1 connector differential pins C2/C3

66AK2L06 transmit output [SHARED_SERDES_0]  JESD channel 1 differential pins AG19/AG18 => ROUTE TO => FMC1 connector differential pins A22/A23

For our ADC: (Using JESD subclass 1, with 122.88MHZ CLOCK with 120KHZ sys ref as generated from EVM)

66AK2L06 receive input  [SHARED_SERDES_0]  JESD channel 0 differential pins AJ18/AJ19 <= ROUTE FROM <= FMC1 connector differential pins C6/C7

66AK2L06 receive input  [SHARED_SERDES_0]  JESD channel 1 differential pins AK19/AK20 <= ROUTE FROM <= FMC1 connector differential pins A2/A3

Bryan Ogilvie

  • Hi Bryan,

    The schematics has a big red circle around these pairs. Is this because these pairs are called out incorrectly in the table inserted in the schematic on sheet 12 of 47?


    No, this is not the case. These are usually placed to emphasize on the connection of the device balls, or add a note for the pcb designers (i.e. something like "place as close to the SoC as possible"), see page 18 of the schematic. In this case, I think the designers of the board wanted to point the attention to the capacitors that are used: 0.1uF_6.3V_10%_X5R_0201.

    lamar process balls AG19/AG18 (schematic signal names JESD1/AIF0_TXP_SOC, JESD1/AIF0_TXN_SOC) drive the JESD switch (U32) at pins 15/16 (schematic signal names JESD1_TXP_FMC1, JESD1_TXN_FMC1) which are then ac coupled to the FMC1 connector pins A22/A23.

    is this correct?


    Yes, this is correct.

    Also, since the JESD switch is used, what do I need to do to set up the Xilinx which generates the multiplexing control on the switch accommodate my JESD lane arrangement on our board with both a DAC and ADC


    Do you need assistance with your software here? If so then I'll consult the sw team about this, as I am not familiar with the 66AK2L devices.

    Best Regards,
    Yordan

     


     Please make sure you read the forum guidelines first.

  • In reply to Yordan Kovachev:

    Hi Yordan, thanks for your assistance.  Yes I guess we need the software guys to tell us how to set up the evm correctly to talk to our ADC/DAC, which we have connected to the EVM with the following connections:

    Our hardware JESD lane setup for our protoboard connected to the EVM:

    For our DAC: (Using JESD subclass1, with 122.88MHZ CLOCK with 120KHZ sys ref as generated from EVM)

    66AK2L06 transmit output [SHARED_SERDES_0]  JESD channel 0 differential pins AH18/AH17 => ROUTE TO => FMC1 connector differential pins C2/C3

    66AK2L06 transmit output [SHARED_SERDES_0]  JESD channel 1 differential pins AG19/AG18 => ROUTE TO => FMC1 connector differential pins A22/A23

    For our ADC: (Using JESD subclass 1, with 122.88MHZ CLOCK with 120KHZ sys ref as generated from EVM)

    66AK2L06 receive input  [SHARED_SERDES_0]  JESD channel 0 differential pins AJ18/AJ19 <= ROUTE FROM <= FMC1 connector differential pins C6/C7

    66AK2L06 receive input  [SHARED_SERDES_0]  JESD channel 1 differential pins AK19/AK20 <= ROUTE FROM <= FMC1 connector differential pins A2/A3

    For the ADC sync:

    66AK2L06 sync input [SOC_JESD_SYNCOUT0_P_FMC1 ] differential pins AJ9/AJ10 => ROUTE TO => FMC1 connector differential pins G12/G13

    For the DAC sync:

    66AK2L06 sync input [SOC_JESD_SYNCIN0_P ] differential pins AG12/AG13 <= ROUTE FROM <= U48 buffer pins 1/2 <= ROUTE FROM <= FMC1 connector differential pins F10/F11

    For the ADC/DAC primary sampling clock: (Using the 122.88MHZ)

    U47  CDCM6208V1RGZR [SYS_CLKP_FMC1 ] differential pins 23/22 => ROUTE TO => FMC1 connector differential pins K4/K5

    For the ADC/DAC system reference strobe: (Using the 120KHZ generated from Xilinx fpga)

    U51  SN65LVDS104PWR [SYSREF_P_FMC1] differential pins 14/13 => ROUTE TO => FMC1 connector differential pins J2/J3

    Can you please verify the lane, clock, and reference setup we are expecting to make sure I read the schematics and your partial reply regarding this.  If our board does not have any problems on the above assignments then what we need from you now is how to accommodate it with the required software drivers needed for the 66ak2l06 as well as any additional setup of Xilinx for switch control needed.

    Bryan Ogilvie

  • In reply to bryan ogilvie:

    Hi Bryan,

    I've notified the K2L team. They will post their feedback directly here.

    Best Regards,
    Yordan

     


     Please make sure you read the forum guidelines first.

  • In reply to Yordan Kovachev:

    Hi Yordan, any feedback on the Jan 2nd note from your guys?  Still having issues and need to make sure the 66AK2L06 EVM JESD lanes, clock, reference, are called out correctly on the connector.  I repeat it here below:

    Our hardware JESD lane setup for our protoboard connected to the EVM:

    For our DAC: (Using JESD subclass1, with 122.88MHZ CLOCK with 120KHZ sys ref as generated from EVM)

    66AK2L06 transmit output [SHARED_SERDES_0]  JESD channel 0 differential pins AH18/AH17 => ROUTE TO => FMC1 connector differential pins C2/C3

    66AK2L06 transmit output [SHARED_SERDES_0]  JESD channel 1 differential pins AG19/AG18 => ROUTE TO => FMC1 connector differential pins A22/A23

    For our ADC: (Using JESD subclass 1, with 122.88MHZ CLOCK with 120KHZ sys ref as generated from EVM)

    66AK2L06 receive input  [SHARED_SERDES_0]  JESD channel 0 differential pins AJ18/AJ19 <= ROUTE FROM <= FMC1 connector differential pins C6/C7

    66AK2L06 receive input  [SHARED_SERDES_0]  JESD channel 1 differential pins AK19/AK20 <= ROUTE FROM <= FMC1 connector differential pins A2/A3

    For the ADC sync:

    66AK2L06 sync input [SOC_JESD_SYNCOUT0_P_FMC1 ] differential pins AJ9/AJ10 => ROUTE TO => FMC1 connector differential pins G12/G13

    For the DAC sync:

    66AK2L06 sync input [SOC_JESD_SYNCIN0_P ] differential pins AG12/AG13 <= ROUTE FROM <= U48 buffer pins 1/2 <= ROUTE FROM <= FMC1 connector differential pins F10/F11

    For the ADC/DAC primary sampling clock: (Using the 122.88MHZ)

    U47  CDCM6208V1RGZR [SYS_CLKP_FMC1 ] differential pins 23/22 => ROUTE TO => FMC1 connector differential pins K4/K5

    For the ADC/DAC system reference strobe: (Using the 120KHZ generated from Xilinx fpga)

    U51  SN65LVDS104PWR [SYSREF_P_FMC1] differential pins 14/13 => ROUTE TO => FMC1 connector differential pins J2/J3

    Can you please verify the lane, clock, and reference setup we are expecting to make sure I read the schematics and your partial reply regarding this.  If our board does not have any problems on the above assignments then what we need from you now is how to accommodate it with the required software drivers needed for the 66ak2l06 as well as any additional setup of Xilinx for switch control needed.

    Bryan Ogilvie

  • In reply to bryan ogilvie:

    Hello, just wanted to let you know we are now talking over the jesd from the 66AK2L06 EVM which indicates our hardware test board attached has all the right assignments to the AD9250 and AD9152 converters. thanks for help.

    Bryan Ogilvie