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RTOS: problem in reset sequence tms320c6678

Other Parts Discussed in Thread: TMS320C6678

Tool/software: TI-RTOS

Hi to all

I made my custom board with 6678 device compatible with EVM. Also I put the spartan 3 same as EVM and programed with EVM bit file. Now the resetz is not coming. Two CDC62005 has clock on their output and clock is coming to DSP but I don't have clock 16.6MHz on DSP sysclock. I measured resetz and see this pin is low always. Can you tell me what parameters have effect on spartan for making resetz to high?

Thank you so much

  • Hi,

    Typically we're not dealing with 3rd party devices.

    Can you show me the relevant part of the schematic. You say this is a custom board, but you load the files for the EVM... Is your board exactly the same as the EVM?

    Best Regards,
    Yordan
  • Hi
    Thanks for your reply.
    Actually as I didn't know what FPGA do, I had to place all EVM circuit in my custom board with some changes. I tested this board before and it worked correctly and I saw 16.6MHz in Sysclkout pin. But now I faced with montage problem in circuit and I don't know how can I find that. As I tested the board, Resetz pin will not be high and put dsp in reset and 16.6 MHz will not come. I don't know why spartan don't send high on Resetz pin. What is the condition for de-asserting Resetz?
    Please help.
  • Hi,

    In Core-Before-IO Power sequencing:
    • RESET may be driven high any time after DVDD18 is at a valid level. In a POR-controlled boot, RESET must be high before POR is driven
    high.

    In IO-Before-Core power sequencing :
    • RESET may be driven high anytime after DVDD18 is at a valid level.

    See Figure 7-3 Core Before IO Power Sequencing (Table 7-2 Core Before IO Power Sequencing) & Figure 7-4 IO Before Core Power Sequencing (Table 7-3 IO Before Core Power Sequencing) in TMS320C6678 Datasheet.

    Best Regards,
    Yordan