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RTOS/TMS320C6678: Does the MessageQ and Notify module use IPCGRx registers to generate interrupts?

Part Number: TMS320C6678

Tool/software: TI-RTOS

Hi,

I read the IPC training document, i.e. http://processors.wiki.ti.com/images/6/69/IPC_Training_2_21.pdf

The page 42 shows the Notify module use 'IPC' to generate interrupt to other DSP cores, does the 'IPC' mean IPCGRx register?

If yes, how do i know SYS/BIOS have been used which SRCRx bits?

My development environment is C6678 + MCSDK.

Thank you,

Snaku

  • Hi Snaku,

    A similar question was answered in the following thread.

    Please take a look and let us know if you still have any questions.

    Best,

    Sahin

  • Hi Sahin,

    Thanks for your reply, I read the post and I am interesting the statement which is "Bit 0 is set to generate interrupt.  Bits 4-7 is set to specify the interrupt generation source. The convention is that bit 4 (SRCS0) is used for core 0, bit 5 (SRCS1) for core 1, etc... .", where can i see the convention in sys/bios source code or documents?

    And I find the Notify module can configure reserve events in .cfg file, e.g. Notify.reservedEvents = 8;, does it limit IPCGR fields usage bits in sys/bios?

    Snaku

  • Hi Snaku,

    Please refer to section 2.4.1 "Inter-Processor Interrupt Registers" of the Chip Interrupt Controller User's Guide:
    www.ti.com/.../sprugw4a.pdf

    I believe it just reserves them for other modules so if you try to use them it will raise an assert, but I will need to ask the development team about this and get back to you.

    Regards,
    Sahin
  • Hi Snaku,

    I heard back from the development team and just wanted to confirm that your initial understanding of the reserve events and IPCGR bit is correct.

    Regards,
    Sahin
  • Hi Sahin,

    Thanks for your support.

    But I need to know which IPCGR fields used by SYS/BIOS, which IPCGR fields still free to use by my application? Can I use 'Notify.reservedEvents' for this purpose?

    Regards,

    Snaku

  • Hi Snaku,

    IPC handles the registers and interrupts for you. Were you planning to generate your own interrupts by writing to the IPCGR registers directly?
  • Hi Sahin,

    Yes, i want to use IPCGRx fields in below function to do synchronization.

    My application runs on sys/bios so i want to make sure this function is no conflict with the MessageQ module.

    /**

    * \brief all cores run this function let core0 to wait other core
    */
    void wait_other_cores()
    {
        U32* msgFlag = (U32*)0x02620240;                // IPCGR0 register address
        U32* msgFlagAK = msgFlag + 0x10;                // IPCAR0 register address
        U32 releaseConter;
        I32 i;

        msgFlag[DNUM] = 0x10;                           // set SRCS0 bit for indication

        while(msgFlag[DNUM])
        {
            if(!DNUM)
            {
                releaseConter = 0;
                for(i=0;i<CORE_NUMBERS;i++){            // core 0 checks all IPCARx SRCC0 bit
                    releaseConter += (msgFlagAK[i] & 0x10);
                }

                if(releaseConter == (0x10 * CORE_NUMBERS)){
                    for(i=0;i<CORE_NUMBERS;i++){        // if all IPCARx SRCS0 bit were set
                        msgFlagAK[i] = 0x10;            // core 0 clear all IPCARx SRCS0 bit
                    }
                }
            }
        }
    }

    thank you,

    Snaku

  • Hi Snaku,

    My comment about Notify.reservedEvents being correlated with the IPCGRx registers was incorrect. The interrupt driver uses the DNUM on the source DSP side to determine which IPCGRx bit is used.

    The IPCGRx bit number = 4 + DNUM

    So for example, if there are 4 DSPS, bits 4-7 are used. Also, bit 31 is used for interrupts from the host.

  • Thanks for your support.

    Snaku