RTOS/TMS320C6678: EMIF-16 NOR FLASH direct booting

Noufal P

Part Number: TMS320C6678

Tool/software: TI-RTOS

Hi all,

Am trying emif-16 nor flash direct booting referring thread https://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/367102

I need some help bringing up direct emif16 norflash booting for my one of the project. Boot pin configuration used : 0x1821.

For the same, i have created a stand alone test application without BIOS.

Am attaching files used in my project. Linker command file content as

-stack 0x400
-heap 0x400

MEMORY
{
BOOT (R): o = 0x70000000 l = 0x00100000
INTVEC (R): o = 0x70100000 l = 0x00001000 /* 512kB LOCAL L2/SRAM */
LOCAL_L2_SRAM: o = 0x00800000 l = 0x00080000 /* 512kB LOCAL L2/SRAM */
LOCAL_L1P_SRAM: o = 0x00E00000 l = 0x00008000 /* 32kB LOCAL L1P/SRAM */
LOCAL_L1D_SRAM: o = 0x00F00000 l = 0x00008000 /* 32kB LOCAL L1D/SRAM */
EMIF16_CS2 (R): o = 0x70101000 l = 0x003FE000
SHRAM (RWIX): o = 0x0C000000 l = 0x00400000 /* 4MB Multicore shared Memory */
EMIF16_CS3: o = 0x74000000 l = 0x04000000 /* 64MB EMIF16 CS3 Data Memory */
EMIF16_CS4: o = 0x78000000 l = 0x04000000 /* 64MB EMIF16 CS4 Data Memory */
EMIF16_CS5: o = 0x7C000000 l = 0x04000000 /* 64MB EMIF16 CS5 Data Memory */
DDR3: o = 0x80000000 l = 0x80000000 /* 2GB CE0 and CE1 external DDR3 SDRAM */
}

SECTIONS
{
.boot > BOOT
{
-l rts6600_elf.lib <boot.obj> (.text)
}
.csl_vect > INTVEC
.intvecs > INTVEC
.text > EMIF16_CS2
.stack > SHRAM
.bss > SHRAM
.cio > SHRAM
.const > EMIF16_CS2
.data > SHRAM
.switch > EMIF16_CS2
.sysmem > SHRAM
.far > SHRAM
.args > SHRAM
.ppinfo > SHRAM
.ppdata > SHRAM

/* COFF sections */
.pinit > EMIF16_CS2
.cinit > EMIF16_CS2

/* EABI sections */
.binit > SHRAM
.init_array > SHRAM
.neardata > SHRAM
.fardata > SHRAM
.rodata > SHRAM
.c6xabi.exidx > SHRAM
.c6xabi.extab > SHRAM
}

Even though i followed mentioned thread, but still my SW is not booting directly from flash. Please help me to sort out the issue.

Regards

Noufal P

over 6 years ago

0 Yordan Kovachev over 6 years ago

TI__Guru**** 161600 points

Hi,

I've notified the RTOS team. They will post their feedback directly here.

Best Regards,
Yordan

0 Rahul Prabhu over 6 years ago

TI__Guru** 114410 points

When the boot fails can you connect to the DSP and see where the program counter is at. EMIF16 NOR boot simply sets up the EMIFA interface and passes control to the instruction at the base of the NOR direct addressing memory.

When you connect to the DSP, can you also open a memory browser and check to see if you can see the boot data at the based of NOR flash direct addressing region.

Regards,
Rahul

0 Noufal P over 6 years ago in reply to Rahul Prabhu

Intellectual 920 points

Hi sir,

thank you for your reply.

i Checked PC reg value, It is showing at Flash address and tried multiple reading. each time it is showing different value in the Flash address region.

Also checked flash content. It is same as the flashed content.

Sorry one Edit,

Flash content is showing as ZEROs if boot mode is EMIF NOR BOOT.

Regards,

Noufal P

0 Rahul Prabhu over 6 years ago in reply to Noufal P

TI__Guru** 114410 points

Noufal,

How did you flash the boot image to the parallel NOR? It is strange that you don`t see the contents of the EMIF NOR as this is XIP mode of execution so you should see the image in the direct addressing region of the NOR flash.

We have an example NOR flash writer that we have provided from the link provided below:
processors.wiki.ti.com/.../KeystoneI_Bootloader_Resources_and_FAQ

Regards,
Rahul

0 Noufal P over 6 years ago in reply to Rahul Prabhu

Intellectual 920 points

Thank you for your reply.
i have a flash writer code. Same writer has been used for flashing image at flash in IIC boot mode. IT was working fine. Am facing problem with NOR-Boot. it would be good if anyone can provide me test application that can be flashed directly to NOR-Flash.

Thanks,
Noufal P

0 Noufal P over 6 years ago in reply to Noufal P

Intellectual 920 points

Hi all,

i have created image using the conversion method provided here. Also done some modification in the command file. please find the attachment for latest command file.

with this, image is not executed as we are not seeing any debug prints on the console. we connected debugger and we can see text segment is being extracted from the image and put it to the locations (flash/L2SRAM/MSMCSRAM) sections as we mentioned in the command file.

Does it mean that RBL is able to identify the image and extract text segment from the image properly but not able to branch to the new location to start the execution.

also help me if am missing any configuration or PLL setting for the system. and is there any register to check if all the PLL configurations are proper or not?

It is so urgent that we are in the middle of project.

C6678 - Copy.txt

/*
 * Do not modify this file; it is automatically generated from the template
 * linkcmd.xdt in the ti.targets.elf package and will be overwritten.
 */

/*
 * put '"'s around paths because, without this, the linker
 * considers '-' as minus operator, not a file name character.
 */


-l"C:\ti\ndk_2_21_01_38\packages\ti\ndk\miniPrintf\lib\miniPrintf.ae66"
-l"C:\ti\ndk_2_21_01_38\packages\ti\ndk\hal\ser_stub\lib\hal_ser_stub.ae66"
-l"C:\ti\ndk_2_21_01_38\packages\ti\ndk\hal\timer_bios\lib\hal_timer_bios.ae66"
-l"C:\ti\ndk_2_21_01_38\packages\ti\ndk\os\lib\os.ae66"
-l"C:\ti\ndk_2_21_01_38\packages\ti\ndk\hal\userled_stub\lib\hal_userled_stub.ae66"
-l"C:\ti\ndk_2_21_01_38\packages\ti\ndk\hal\eth_stub\lib\hal_eth_stub.ae66"
-l"C:\ti\ndk_2_21_01_38\packages\ti\ndk\tools\cgi\lib\cgi.ae66"
-l"C:\ti\ndk_2_21_01_38\packages\ti\ndk\tools\hdlc\lib\hdlc.ae66"
-l"C:\ti\ndk_2_21_01_38\packages\ti\ndk\tools\console\lib\console_min.ae66"
-l"C:\ti\ndk_2_21_01_38\packages\ti\ndk\netctrl\lib\netctrl.ae66"
-l"C:\ti\ndk_2_21_01_38\packages\ti\ndk\nettools\lib\nettool.ae66"
-l"C:\ti\ndk_2_21_01_38\packages\ti\ndk\tools\servers\lib\servers_min.ae66"
-l"C:\ti\ndk_2_21_01_38\packages\ti\ndk\stack\lib\stk6_ppp_pppoe.ae66"
-l"C:\ti\pdk_C6678_1_1_2_5\packages\ti\transport\ndk\nimu\lib\debug\ti.transport.ndk.nimu.ae66"
-l"C:\ti\pdk_C6678_1_1_2_5\packages\ti\platform\evmc6678l\platform_lib\lib\debug\ti.platform.evm6678l.ae66"
-l"C:\ti\pdk_C6678_1_1_2_5\packages\ti\drv\pa\lib\ti.drv.pa.ae66"
-l"C:\ti\pdk_C6678_1_1_2_5\packages\ti\drv\cppi\lib\ti.drv.cppi.ae66"
-l"C:\ti\pdk_C6678_1_1_2_5\packages\ti\drv\qmss\lib\ti.drv.qmss.ae66"
-l"C:\ti\pdk_C6678_1_1_2_5\packages\ti\csl\lib\ti.csl.ae66"

--retain="*(xdc.meta)"


--args 0x0
-heap  0x0
-stack 0x1000

MEMORY
{
    L2SRAM (RWX) : org = 0x800000, len = 0x80000
    MSMCSRAM (RWX) : org = 0xc000000, len = 0x400000
    DDR3 (RWX) : org = 0x80000000, len = 0x20000000
}

/*
 * Linker command file contributions from all loaded packages:
 */

/* Content from xdc.services.global (null): */

/* Content from xdc (null): */

/* Content from xdc.corevers (null): */

/* Content from xdc.shelf (null): */

/* Content from xdc.services.spec (null): */

/* Content from xdc.services.intern.xsr (null): */

/* Content from xdc.services.intern.gen (null): */

/* Content from xdc.services.intern.cmd (null): */

/* Content from xdc.bld (null): */

/* Content from ti.targets (null): */

/* Content from ti.targets.elf (null): */

/* Content from xdc.rov (null): */

/* Content from xdc.runtime (null): */

/* Content from ti.targets.rts6000 (null): */

/* Content from ti.sysbios.interfaces (null): */

/* Content from ti.sysbios.family (null): */

/* Content from ti.sysbios (null): */

/* Content from xdc.services.getset (null): */

/* Content from ti.sysbios.hal (null): */

/* Content from ti.sysbios.knl (null): */

/* Content from ti.csl (null): */

/* Content from ti.drv.qmss (null): */

/* Content from ti.drv.cppi (null): */

/* Content from ti.drv.pa (null): */

/* Content from ti.platform.evmc6678l (null): */

/* Content from ti.transport.ndk (null): */

/* Content from ti.ndk.rov (null): */

/* Content from ti.sysbios.family.c66 (null): */

/* Content from ti.sysbios.family.c64p (null): */

/* Content from ti.sysbios.family.c66.tci66xx (null): */

/* Content from ti.ndk.config (null): */

/* Content from ti.drv.srio (null): */

/* Content from ti.sysbios.gates (null): */

/* Content from ti.sysbios.heaps (null): */

/* Content from xdc.runtime.knl (null): */

/* Content from ti.sdo.ipc.interfaces (null): */

/* Content from ti.sysbios.syncs (null): */

/* Content from ti.sdo.ipc.family (null): */

/* Content from ti.sdo.utils (null): */

/* Content from ti.sysbios.xdcruntime (null): */

/* Content from ti.sysbios.family.c62 (null): */

/* Content from ti.sysbios.timers.timer64 (null): */

/* Content from ti.sysbios.family.c64p.tci6488 (null): */

/* Content from ti.ndk.config.family (null): */

/* Content from ti.sysbios.utils (null): */

/* Content from ti.catalog.c6000 (null): */

/* Content from ti.catalog (null): */

/* Content from ti.catalog.peripherals.hdvicp2 (null): */

/* Content from xdc.platform (null): */

/* Content from xdc.cfg (null): */

/* Content from ti.platforms.generic (null): */

/* Content from TCCMSMC6672 (null): */

/* Content from ti.sdo.ipc (ti/sdo/ipc/linkcmd.xdt): */

SECTIONS
{
    ti.sdo.ipc.SharedRegion_0:  { . += 0x10000;} run > 0xc000000, type = NOLOAD
}


/* Content from ti.sdo.ipc.family.c647x (null): */

/* Content from ti.sdo.ipc.notifyDrivers (null): */

/* Content from ti.sdo.ipc.transports (null): */

/* Content from ti.sdo.ipc.nsremote (null): */

/* Content from ti.sdo.ipc.heaps (null): */

/* Content from ti.sdo.ipc.gates (null): */

/* Content from configPkg (null): */


/*
 * symbolic aliases for static instance objects
 */
//xdc_runtime_Startup__EXECFXN__C = 1;
//xdc_runtime_Startup__RESETFXN__C = 1;
//TSK_idle = ti_sysbios_knl_Task_Object__table__V + 144;

SECTIONS
{
    .text: load > L2SRAM
    .ti.decompress: load > MSMCSRAM
    .stack: load > MSMCSRAM
    GROUP: load > MSMCSRAM
    {
        .bss:
        .neardata:
        .rodata:
    }
    .cinit: load > MSMCSRAM
    .pinit: load >> MSMCSRAM
    .init_array: load > MSMCSRAM
    .data: load >> MSMCSRAM
    .fardata: load >> MSMCSRAM
    .switch: load >> MSMCSRAM
    .sysmem: load > MSMCSRAM
    .far: load >> MSMCSRAM
    .args: load > MSMCSRAM align = 0x4, fill = 0 {_argsize = 0x0; }
    .cio: load >> MSMCSRAM
    .ti.handler_table: load > MSMCSRAM
    sharedL2: load >> MSMCSRAM
    systemHeap: load >> MSMCSRAM
    .cppi: load >> MSMCSRAM
    .qmss: load >> MSMCSRAM
    .code: load >> MSMCSRAM
    .vecs: load >> MSMCSRAM
     platform_lib: load >> MSMCSRAM
    .far:taskStackSection: load >> MSMCSRAM
     .resmgr_memregion: load >> MSMCSRAM align = 0x80
    .resmgr_handles: load >> MSMCSRAM align = 0x10
    .resmgr_pa: load >> MSMCSRAM align = 0x8
    .far:IMAGEDATA: load >> MSMCSRAM align = 0x8
    .far:NDK_OBJMEM: load >> MSMCSRAM align = 0x8
    .far:NDK_PACKETMEM: load >> MSMCSRAM align = 0x80
    xdc.meta: load >> MSMCSRAM, type = COPY
}

Regards,

Noufal P

0 Noufal P over 6 years ago in reply to Noufal P

Intellectual 920 points

Dear all,
Can anyone please help me regarding EMIF16 boot on TMS320C6678 DSP.

Regards,
Noufal P

0 Rahul Prabhu over 6 years ago in reply to Noufal P

TI__Guru** 114410 points

Noufal,

You earlier indicated that you are trying to direct EMIF16 boot mode. Is this not the case any more? your linker command file places all of the EMIF16 code sections in MSMC and L2 memory.

When you boot and the boot fails, connect to the DSP, place the entry point of your application into the DSP PC and see if the application starts running. If that is the case then most likely, the ROM is unable to detect the entry point of the application. Another thing to try is to connect to the DSP without any default GEL files and then load the Debug GEL from here and test the SOC and ROM status.

processors.wiki.ti.com/.../Keystone_Device_Architecture

copy the log from that GEL into a text file and attach it to your response.

Regards,
Rahul

0 Rahul Prabhu over 6 years ago in reply to Rahul Prabhu

TI__Guru** 114410 points

Does your boot image appear, like this in CCS format. Can you try the image attached with your setup and let me know if this works with your setup:

xip.cs3.le.ccs

Note this image is for EMIF CS3 so you may have change in base address depending on which CS you are using.

Regards,

Rahul

0 Noufal P over 6 years ago in reply to Rahul Prabhu

Intellectual 920 points

Dear Rahul,

I have modified ccs file based on my CS2 base address (0x70000000). and converted to bin using ccs2bin.

After flashing am not seeing anything on console and can you please tell me what will be the observation for this image.

While checking debugger PC keep on changing in 0x7xxxxxxx address.

Also does this image required swapping (using swap16.exe) before generating bin file.?? or we need to enable swap option while flashing this image???

Please let us know the text section address of your application so that we can change the PC and try out .

Regards,

Noufal P

0 Noufal P over 6 years ago in reply to Noufal P

Intellectual 920 points

Dear Rahul,

Following are the observation of your ccs image using debugger.
1. Since our CS base address is 0x7000_0000 and we modified this in the first line of your ccs image and convereted to bin using ccs2bin.exe.
2. We seen that after power on, RBL jump to 0x7000_0000 and executed few instruction and jumps to 0x7400_0000.
But in our nothing is there at 0x7400_0000 location, it looks like though we changed 0x7400_0000 to 0x7000_0000 in the first line of your ccs image still there may be some sections in your linker file/code which is trying to execute in 0x7400_0000.
3. It would be great if you share your project file using which you had created ccs image. so that we can modify the flash setting and rebuild and try in our setup.

Thanks in advance
Noufal P

0 Rahul Prabhu over 6 years ago in reply to Noufal P

TI__Guru** 114410 points

Noufal,

Unlike C6657, the C6678 device doesn`t allow for choosing a different CS# base address to branch to. the default branch address for this device is always CS2 base address which is 0x7000_0000. If you hook the NOR flash to CS3, we recently found that the ROM reads 0xffff_ffff from 0x7000_0000 address and keep executing in the slow memory until it eventually rolls over to CS3 addressing region after around 18 seconds.

to avoid this long start up delay, you should connect the parallel NOR to CS2 so it can branch to application at address 0x7000_0000 correctly .

Regards,
Rahul

0 Noufal P over 6 years ago in reply to Rahul Prabhu

Intellectual 920 points

My issue got resolved by visiting TI. The way we are converting .out to binary image was wrong.
Thanks everyone for their suggestions. :)

Regards,
Noufal P

0 Vasantha Kungarupalayam over 5 years ago in reply to Noufal P

Prodigy 30 points

Could you post the steps for converting .out to Bin Steps, as we are trying to boot the same config?

0 Noufal P over 5 years ago in reply to Vasantha Kungarupalayam

Intellectual 920 points

you can refer www.ti.com/.../sprabl5.pdf document.

Processors

Processors forum

RTOS/TMS320C6678: EMIF-16 NOR FLASH direct booting