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CCS/TMS320C6678: kicker mechanism for IPCGR in C6678

Xu Wang
Prodigy 70 points
Part Number: TMS320C6678

Tool/software: Code Composer Studio

I use IPCGR for IPC interrupt. In my project, two cores, say core A and core B, may both send interrupts to Core C. In the C6678 Datesheet, it is said that before I can write the IPCGR register, I must unlock the kicker mechanism, My question is: what occur if core A and core B try to unlock the kicker mechanism simultaneous? I guess there are two possible cases.

Case 1:  KICK0 and KICK1 registers do not care who unlock the kicker mechanism. Once it is unlocked by either core, the IPCGR register become writable. Then core A and core B can both write the IPCGR register for core C. In this case, will core C miss one of the interrupts?

Case 2:  KICK0 and KICK1 registers know who unlock the kicker mechanism. If core A unlock it, then core B can not unlock it again until Core A lock the kicker mechanism. If this is true, the following scenario may occur: Core A unlock the kicker --> Core B try to unlock the kicker, but is blocked. So Core B will halt  --> Core A lock the kicker --> Core B resume its execution and unlock the kicker. 

Which case is true in C6678?  Thank you.

Best wishes!

  • 0
    TI__Guru 65405 points
    The team is notified. They will post their feedback directly here.

    BR
    Tsvetolin Shulev
  • 0 in reply to Cvetolin Shulev-XID
    TI__Mastermind 43296 points
    Hi Xu,

    It is the case - KICK0 and KICK1 registers do not care who unlock the kicker mechanism. Once it is unlocked by either core, the IPCGR register become writable.

    In the ISR of core C, you can scan the IPCAR0-7 to process without missing any interrupt.

    Regards,
    Garrett
  • 0 in reply to Garrett Ding
    Prodigy 70 points

    Thank you for your help. In your reply, you said that "scan the IPCAR0-7 to process without missing any interrupt". Let us assume that the coreID of core C is 7, and Core A and Core B use SRCC0 and SRCC1 as their Source IDs for the IPCAR register respectively. According to my understanding, the following case may occur:


    Core A unlocks the kicker mechanism --> Core A writes IPCGR7, sets the IPCG bit and the SRCS0 bit --> Core C receives the interrupt, enters the interrupt service routine (ISR). The hardware clears the GIE bit automatically. --> Since the kicker mechanism is unlocked, Core B can write IPCGR7 directly, set the IPCG bit and the SRCS1 bit. --> Since the GIE bit is cleared, the current ISR in Core C will not be interrupted by the interrupt from Core B. But the SRCC1 bit has been set. So in the ISR, Core C can scan the IPCAR7 register to check if the SRCC1 bit is set. In this way, Core C will not miss the interrupt from Core B.


    Do I understand it correctly? Thank you.


    Best wishes!


    Xu Wang

  • 0 in reply to Xu Wang
    TI__Mastermind 43296 points
    Hi Xu,

    Yes, you made it more clear : -)

    Regards,
    Garrett