Other Parts Discussed in Thread: PROCESSOR-SDK-C667X
I am using a custom board based on TI's keystone I architecture(c6678) and trying to come up with a simple boot process to boot the core 0.
set up:
The board is configure to be in ROM ethernet boot (EMAC boot) mode. So the dsp chip on the board periodically sends dhcp request, i think its a specialized dhcp request. I have something on a linux host that listen for that request and pushes the boot image thats converted to ethernet packet format to the board. I am using the tools from TI to convert the .out file to a boottable and from boottable to an ethernet packet formatted image. Everything works fine if the image fits into the L2 SRAM.
The problem and requirement:
Our image is big so it needs to be loaded into DDR3. However, the DDR3 is not yet initialized when the image is pushed. The boot manual from our vendor and TI's boot manual both proposed a two stage boot in which the stage 1 image initializes the ddr3 and goes back to ROM boot software , then the actual production image is pushed. I have tested this and it worked.
However, we prefer this boot process to be done in a single step. We have also ruled out writing the ddr3 init code into the flash so that the DSP can run the code from flash to initialize DDR3 at reset before going into the ROM boot software. This is not desired because it requires a human to burn the ddr3 init code into the flash. The bottom line is that , when we get a board from our vendor, we want to just be able to plug it into the chassis and everything boots okay. To achieve this, we need to be able to initialize DDR3 in a single booting process.
After some research , i found that if i place the emif4 configuration structure inside a special piece of memory using #pragma and the right linker command file setting , the boot software will be able to initialize the ddr3 before loading anything into the DDR3. I have checked the datasheet , i am confused to where i need to place the structure. Memory Map Table 2-2 in SPRS691E seems to suggest that i should put the structure in 0x21000000
However, Table 2-3 in Section 2.4 in SPRS691E has another local section in L2 for DDR configuration table (0x00837500) ,
My question now is , which one should I place the emif config table in (BOOT_EMIF4_TBL_T defined in "tiboot_c66x.h" shipped with mcsdk2.0)?
After some reseach, according to the this post,.
in the SPI boot example, the DDR3 configurable structure should be placed in the L2 reserved section , namely the section start at 0x00837500, is that correct?
if yes, i have tried both, neither have seemed to work.
my linker command file is looking like that,
c -heap 0x6000 -stack 0x3000 /* Memory Map (Symmetric Default) */ MEMORY { /* External DDR3 Memory */ DDR3: o = 0x80000000 l = 40000000h //DDR_CFG: o = 0x21000000 l = 000001ffh //MSMCSRAM: o = 0xc000000, len = 0x400000 /* Local (Aliased) Core Memory * Use for shared code and data */ /*LOCAL_L1D: o = 00f00000h l = 00008000h LOCAL_L1P: o = 00e00000h l = 00008000h LOCAL_BOOT_RSVD2: o = 00873600h l = 00000c980h LOCAL_DDR_CFG: o = 00873500h l = 00000100h LOCAL_BOOT_RSVD: o = 00872E00h l = 00000700h LOCAL_L2: o = 00802000h l = 00070E00h LOCAL_PARAM_TAB: o = 00800200h l = 00001E00h LOCAL_BOARD_INFO: o = 00800100h l = 00000100h LOCAL_INT_VECT: o = 00800000h l = 00000100h } SECTIONS { .csl_vect > CORE0_L2 .text > DDR3 .switch > CORE0_L2 .const > CORE0_L2 .cinit > CORE0_L2 .neardata > CORE0_L2 .rodata > CORE0_L2 .bss > CORE0_L2 .fardata > CORE0_L2 .far > CORE0_L2 .stack > CORE0_L2 .sysmem > CORE0_L2 .cio > CORE0_L2 //.ddrCfgTable > CORE0_DDR_CFG .extData > CORE0_L2 }
My emif4 configuration table looks like this,
/******************************************************************************* * Emif4 (DDR3) configuration table *******************************************************************************/ #pragma DATA_SECTION(".ddrCfgTable") BOOT_EMIF4_TBL_T ddrCfgTable ={ BOOT_EMIF4_ENABLE_pllCtl| BOOT_EMIF4_ENABLE_sdRamRefreshCtl| BOOT_EMIF4_ENABLE_sdRamTiming1| BOOT_EMIF4_ENABLE_sdRamTiming2| BOOT_EMIF4_ENABLE_sdRamTiming3| BOOT_EMIF4_ENABLE_ddrPhyCtl1, 1, 20, 2, 0x63222B32, 0, 0x00001450, 0x1113783c, 0x30b37fe3, 0x559f8adf, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x0010010C, 0, 0, 0, 0, 0, 0, 0, 0 };
any insight/comment on this boot process is much appreciated. thanks.