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TMS320C6655: TMS320C6655

Part Number: TMS320C6655
Other Parts Discussed in Thread: UCD9222, UCD7242

Here is a description of the problem we’re facing on our board.

 -          The board (reference 01BRD20209-105 for the latest revision) is quite complex but the issue we’re talking is located on the “DSP” of the board, based on a TI TMS320C6655.

-          This DSP requires a specific powering scheme for its core with two separated rail: CVDD and 1.0V. CVDD must be dynamically set to a specific value between 0.9V and 1.1V suing 4 signals coming from the DSP itself. TI requires this behavior in order to adapt the powering to each specific part.

-          In order to achieve this behavior, we almost copied the reference design from TI (C6657EVMLite) using UCD9222RGZ + UCD7242RSJ chips.

-          The UCD9222 chip is a programmable controller on which we used the same programming file as TI does on the EVMLite. We just had to make an update, as told by TI support, to enable the automatic voltage setting since the original file provided by TI disabled the feature on the EVMLite due to an hardware bug (it’s a bit surprising!).

-          Remark: we used this reference design for CC6657 which is a dual core. So the power supplies are over-rated for a single core device such as C6655.

-          These controllers are enabled/disabled by a PLD on the board that acts as the power sequencing master for all the processors on the board. This component, upon power-up, starts all the DC/DC converters of the board (a lot) and check for the Power-Good signals coming from all rails. If any of them fail the PD start the power-down sequence of all rails and then try to start again.

-          During all the prototyping tests of the board we never had issues with the design. The problems appeared later during production with a few percent of the boards failing (out of several thousands).

-          Description of the failure:

  • The board is cycling continuously ON and OFF because a power-good signal is not OK.
  • When investigating, the power-good signal is always on the two signals from the UCD9222 (it’s a dual controller for each rail of the DSP’s core).
  • When further investigating (by connecting an I2C probe on the chip for interrogation during power-up), it seems that the UC9222 is triggering an “medium overcurrent” on CVDD rail fault when trying to ramp-up its voltage and we can see at the scope that the voltage ramp up to 0.85V then stop. If we try to make a “hot” restart of the chip using the I2C interface, the fault flag is triggered in the same way.
  • We can’t measure a true short-circuit on the failing rail.
  • The problem is always triggered at power-up, never on a running board.
  • Temperature and time between ON and OFF events have no influence on the problem.
  • We can see, on failing boards, that the static impedance on both rails seems to be lower:
    • On a good board, R(1.0V) is about 64 ohms. On a failed board its lower than 40 ohms
    • On a good board, R(CVDD) is about 20 ohms. On a failed board its lower than 10 ohms
  • When replacing the power part (UCD7242) sometimes it solves the problem and sometimes not!
  • On failed boards, PSI Control made some X-Ray analysis and we never detect soldering issues

-          I checked recently the status of all documentation from TI (errata sheets, datasheets, manuals, application notes, ..) and nothing has changed since the beginning of the design (2015).

 

As you can understand, it’s a tricky issue where we try a lot of things. Everything seems located between the DSP itself and the two power chips.

 

We can share more information (schematic and PCB design) 

  • The team is notified. They will post their feedback directly here.

    BR
    Tsvetolin Shulev
  • Johan,

    I posted a response but it appears to have been lost.

    Please provide a block diagram of your power solution.  Do not post anything proprietary.  Show the modules and also the control mechanism for the power sequencing.  Also, show the method for sequencing the the clocks and controlling the resets.

    The UCD9222 monitors faults from the power stages like the UCD7242.  Do you see the fault from the UCD7242 toggle?  It also monitors the current and temp inputs.  Are these properly connected and configured?

    The UCD7242 provides a very high density power solution.  As such, the package is small and the currents large.  The implementation of the copper around the UCD7242 can impact its performance.  Please provide an image of the PCB layout in the area of the UCD7242.  How thick is this copper?

    Tom

  • Here are some technical details:

     

    -          Attached schematic sheet with this part of the power supplies

     

    -          Power Sequencing is done as follows: when the board is powered up (+12V applied from AC/DC adapter), the sequencer (PLD) wait for 1 second before starting the power-up sequence, then:

    • UCD9222_nRESET is released
    • Peripheral 1.8V is enabled
    • Wait 8ms
    • UCD9222_EN1 is set to 1
    • Wait 8ms
    • UCD9222_EN2 is set to 1
    • Wait 8ms
    • DDR3 1.5V is enabled
    • Wait 128ms
    • Enable DSP’s clocks
    • Start Resetting DDR3
    • Wait 8ms
    • End Resetting DDR3
    • Release DSP-nPOR
    • Wait 4ms
    • If right now both UCD9222_PG1 and UCD9222_PG2 are not OK, start the power-down sequence
    • If both PG signals are OK, the DSP is controlled by:
      • nRESET, which is always 1
      • nRESETFULL, which is handled by another CPU on the board and release later

     

    -          The PCB is a 10 layers 1.6mm FR4 board. Here are some views:

     

    • Global view form the top: UCD9222 is on Bottom layer (Blue – bottom left of picture) and UCD7242 is on Top Layer (Red – IC5 top left of picture) with all power components (capacitors, inductors)

     

     

    • Zoom view of UCD7242 alone

     

     

    • Ground planes: 4 fully complete ground planes are covering the board
    • Copper: 18µm inner layers, 12µm with end thickness 30µm outer layers

     01BRD20209-105 DSP Core Power Supplies - Schematic.pdf

  • Johan,

    You stated that you used the same configuration file as the EVM, other than enabling AVS.  You should have used the Fusion Digital Power Designer program to update your configuration in accordance to the components used in your assembly.  We have found that power supply stability can be strongly affected when components are changed.  Please use this program to update the config file loaded into the UCD9222.  You will need to carefully update the schematic in the GUI tool to properly reflect the components installed.

    You did not respond to my question about faults from the UCD7242.  Do you see this pin changing state?  Does it toggle each PWM clock period or does it transition solid into the failure indication?

    You mention that the power supply will run steady once it achieves successful start-up.  Please post a scope capture of the PWM control signal for the supply rail that occasionally fails when it is operating stable in regulation.  Is it the same or different from the PWM control seen on a board that never fails?  If different, please post an image of the PWM signal on a board that does not fail.  You will need to enable some scope persistence so that the capture will show the control loop in operation.

    Tom

  • Johan,
    Any update to this thread?
    Tom
  • Johan,

    Please provide an update or this thread will be closed.

    Tom