Hi,
We are adding PCIe to our design to facilitate high bandwidth data between a TI DSP and Xilinx FPGA. In order to prototype the design, we're using a TMDSEVM6657LS eval board in RC mode connected to a Xilinx KCU116 Kintex Ultrascale+ board in EP mode. The DSP code is based on the PCIe example design using PDK C665x V2.08. The PCIe link is Gen2 x2.
The link initializes properly and both sides report 'link up'. Furthermore, I can successfully read and write FPGA memory from the DSP. The problem is pushing data from the FPGA to the DSP. If I send a Requester Request TLP with one data word from the FPGA, I get no indication at the DSP that anything has happened. If I send a TLP with two data words from the FPGA, I get a fatal error indication at the DSP. No data is received in my Rx buffer in either case. I have scoured the TI documentation, TI forums and internet in general and have have seen many interesting and relevant articles, but none points to a cause or even changes my symptoms.
Here's my general DSP setup:
CMD_STATUS = 0x07 // IB & OB address translation enabled, LTSSM enabled
STATUS_COMMAND = 0x00100146 // enable response to memory accesses
MEMSPACE = 0x00900080 // points to 1MB L2 SRAM, 32 bit addressing
PREFETCH_MEM = 0x00900080 // same as MEMSPACE
BAR1 (mask) = 0x0FFFFFFF
BAR1 = 0x90000000 // arbitrary inbound PCIe address
IB_BAR0 = 1 // use BAR1
IB_START0_LO = 0x90000000
IB_START0_HI = 0 // 32-bit addressing
IB_OFFSET0 = 0x00863C00 // address of my Rx buffer in L2 SRAM
On the FPGA side, bus master capability has been enabled. While I cannot see the actual serial data generated by the FPGA, the Requester Request TLP for a two word write to 0x90000000 looks correct.
Any suggestions as to what might be wrong with my configuration would be greatly appreciated.
Thanks,
Stuart