ISR execution on Core1 rather than Core0

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BR
Tsvetolin Shulev

Hi Nicolas,

The example in processors.wiki.ti.com/.../Configuring_Interrupts_on_Keystone_Devices
may help figure out how to configurre an ISR to be executed in Core1. In the example, essentially the eventId is configured to 0x15 (=21), which is CIC0_OUT(32+0+11*n), see Figure 7-32 Interrupt Controller outputis TMS320C6678 System Event Inputs — C66x CorePac Primary Interrupts.

The system interrupt (CSL_INTC0_VUSR_INT_O = 0x6F = 111), see Table 7-38 CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (Sheet 3 of 5) is mapped to channel 32 + (11 * CoreNumber) = 43 for Core0, thus for core 1 this would be 32 + 11*2 = 54.

/* Map System Interrupt to Channel. */
/* Note that hyplnk_EXAMPLE_INTC_OUTPUT = 32 + (11 * CoreNumber) = 43 for Core0*/
CSL_CPINTC_mapSystemIntrToChannel (hnd, CSL_INTC0_VUSR_INT_O, hyplnk_EXAMPLE_INTC_OUTPUT);

You should be able to follow the mechnism to trigger ISR in core 1 only. Instead of CSL_INTC0_VUSR_INT_O, you can configure any CIC0 event you are going to use by updating your
#define CIC0_SYSTEM_INT_ECAT 8
#define CIC0_HOST_INT_ECAT 8

Regards,
Garrett

Hi Garrett,

Thanks for your help.
I have read the example and I think I understood it.
The point is the following: I don't know which value to put in these defines instead to fit my C6657.

As the TMS320C6657 Data Manual (SPRS814A) lists in table 7-34 (CIC0 Event Inputs), I am fixed to CIC0 Input Event #8, which is GPINT24, because the interrupt signal is tied to that pin. So as far as I understand, my define CIC0_SYSTEM_INT_ECAT must remain 8.

In the same manual in table 7-33 (C66x CorePac Primary Inputs), I see CIC0_OUT(8+20*n), where n is the Core number. If the number of CIC0_OUT is referred to by CIC0_HOST_INT_ECAT then, in my understanding, setting it to 8 would be triggering Core0, whereas 28 would trigger Core1. Is that correct?

When setting define CIC0_HOST_INT_ECAT to 28, two problems arise. First, when calling CpIntc_getEventId(CIC0_HOST_INT_ECAT) I receive -1. For a value of 8 I receive 30, which is what I would expect when looking at table 7-33. Second, the ISR is not executed at all, neither on Core0 not on Core1. I expect this to be caused by a failed initialization symbolized by an eventID of -1. So 28 seems not to be the right value.
What else is the right value?
Or is there a mistake somewhere else?

Regards, Nicolas

Hi Nicolas,

>>in my understanding, setting it to 8 would be triggering Core0, whereas 28 would trigger Core1. Is that correct?
Yes, that is correct.

The CpIntc_getEventId() is implemented in bios_6_52_00_12\packages\ti\sysbios\family\c66\tci66xx\CpInt.c and the host interrupt to event mapping structure is in CpIntc.xs, which shows:

"TMS320C6657": {
baseAddr: 0x02600000,
numSystemInterrupts: 208,
numHostInterrupts: 48,
numCores: 2,
numCpIntc: 3,
gemEventsForHostInts: {
22: [0, 20],
23: [1, 21],
24: [2, 22],
25: [3, 23],
26: [4, 24],
27: [5, 25],
28: [6, 26],
29: [7, 27],
30: [8, 28],

So, with either 8 or 28, you should get 30. Have you tried to hard code the IntECATParams.eventId = 30; with CIC0_HOST_INT_ECAT = 28.

The CpIntc_getEventId( ) is pretty straight forward as:

Int CpIntc_getEventId(UInt hostInt)
{
extern volatile cregister UInt32 DNUM;
UInt i;

for (i = 0; i < CpIntc_numEvents; i++) {
if (hostInt == [DNUM][i]) {
return (CpIntc_eventId[i]);
}
}

return (-1);
}

Regards,
Garrett

Hi Garret,

Thanks again for your answer. I just tried what you suggested.
By setting
#define CIC0_HOST_INT_ECAT 28
and exucuting
eventId = CpIntc_getEventId(CIC0_HOST_INT_ECAT);
the resulting eventId is -1 (and not 30).
Manually setting
IntECATParams.eventId = 30;
and calling
IntECATHwi = Hwi_create(CPUINT_ECAT, &CpIntc_dispatch, &IntECATParams, &eb);
still makes no difference, the ISR is not executed.
I'm now trying to debug the code line by line, but do not expect to find anything obviously wrong.
Any further suggestions?

Regards,
Nicolas

I've found something. It is not resolving my problem, but it might be a start.

The function "Int CpIntc_getEventId(UInt hostInt)" in CpInt.c searches for the eventID corresponding to the HostInt.
As I have defined my HostInt "CIC0_HOST_INT_ECAT " to be 28, I assume that the for-loop in this function repeats until "i" is 28. Then, the corresponding eventID should be found and the function should return.
But using the debugger I have observed that after i = 19 the function aborts and returns a -1. I just printed "CpIntc_numEvents" to console and it said that it is 20. So this function is not able to return anything useful for values of HostInt above 19.
--> Since the function never compares a HostInt of 28 with a connresponding eventID, no result can be found and the function returns -1.
Can/should I change this value of "CpIntc_numEvents" somewhere?

I use TI Processor SDK 4.2.0.9 with BIOS v6.52.00.12. The file CpInt.c is contained in C:\ti\bios_6_52_00_12\packages\ti\sysbios\family\c66\tci66xx.

As mentioned earlier, this issue does not fix my problem, because when assigning a hardcoded evendId of 30 to the Params, the ISR is still not executed.

Forget that post I just wrote. I've not read close enough to understand whats happening.

There seems to be a total of 20 Events existing in my project and the function "Int CpIntc_getEventId(UInt hostInt)" tries to find the corresponding Event for a given HostInt. When the HostInt is not found, a -1 is returned instead.

This function goes through all existing Events and does not find any HostInt with a value of 28.

>>There seems to be a total of 20 Events existing in my project.
Not quite follow this, have you tried to use the configuration 22: [0, 20]?

#define CIC0_SYSTEM_INT_ECAT 8
#define CIC0_HOST_INT_ECAT 20

And IntECATParams.eventId = 22;

Regards,
Garrett

I just tried to use
#define CIC0_SYSTEM_INT_ECAT 8
#define CIC0_HOST_INT_ECAT 20
#define CPUINT_ECAT 9
and
IntECATParams.eventId = 22;
but without success. The eventID given by the getter function still returns -1 and the ISR is not executed, neither on Core0 nor on Core1.

Hi,

For C6657, CIC0_8 for core 0, or CIC0_28 for core 1, should be gotten event ID 30. If the way to use SYSBIOS didn't work, are you willing to to try the CSL style code? We have some code example under pdk_c665x_2_0_x\packages\ti\boot\examples\pcie\pcieboot_interrupt\src. For the C6678, the code used secondary interrupt 50 (pice_int_a) for host interrupt 63 (CIC0_3 for core0, CIC0_11 foe core1). You can use C6657 do the same way (use your own interrupt number, just try the CSL styple code)?

Regards, Eric

Hi,

I tried to follow the CSL example from processors.wiki.ti.com/.../Configuring_Interrupts_on_Keystone_Devices and adopted ideas from your suggested example. Now, I came up with the following CSL-style code (replacing the old code from the first post):
CSL_CPINTC_Handle hnd;
CSL_IntcContext intcContext;
CSL_IntcEventHandlerRecord EventHandler[30];
CSL_IntcObj intcObj;
CSL_IntcHandle hTest;
CSL_IntcGlobalEnableState state;
CSL_IntcEventHandlerRecord EventRecord;
CSL_IntcParam vectId;
int eventID = 30;

intcContext.eventhandlerRecord = EventHandler; // INTC module initialization
intcContext.numEvtEntries = 5;
CSL_intcInit(&intcContext);
CSL_intcGlobalNmiEnable(); // Enable NMIs
CSL_intcGlobalEnable(&state); // Enable global interrupts
vectId = CPUINT_ECAT; // Open the INTC Module for Vector ID: CPUINT_ECAT and Event ID
hTest = CSL_intcOpen (&intcObj, eventID, &vectId , NULL);
EventRecord.handler = IsrECAT; // Register an call-back handler which is invoked when the event occurs.
EventRecord.arg = (void *)eventID;
CSL_intcPlugEventHandler(hTest, &EventRecord);
CSL_intcHwControl(hTest, CSL_INTC_CMD_EVTCLEAR, NULL); // Clear the event in case it is pending
CSL_intcHwControl(hTest, CSL_INTC_CMD_EVTENABLE, NULL); // Enabling the events.
hnd = CSL_CPINTC_open(0); // Open the handle to the CPINT Instance
CSL_CPINTC_disableAllHostInterrupt(hnd); // Disable all host interrupts.
CSL_CPINTC_setNestingMode (hnd, CPINTC_NO_NESTING); // Configure no nesting support in the CPINTC Module.
CSL_CPINTC_clearSysInterrupt (hnd, CSL_INTC0_VUSR_INT_O); // Clear system interrupt
CSL_CPINTC_mapSystemIntrToChannel (hnd, CIC0_SYSTEM_INT_ECAT, CIC0_HOST_INT_ECAT); // We now map System Interrupt to channel
CSL_CPINTC_mapChannelToHostInterrupt(hnd, CIC0_HOST_INT_ECAT, CIC0_HOST_INT_ECAT);
CSL_CPINTC_enableSysInterrupt (hnd, CIC0_SYSTEM_INT_ECAT); // We now enable system interrupt
CSL_CPINTC_enableHostInterrupt (hnd, CIC0_HOST_INT_ECAT); // We enable host interrupts.
CSL_CPINTC_enableAllHostInterrupt(hnd); // Enable all host interrupts also.

Result: none of my ISRs is executed any more.
Seems like this code completely destroys the execution of ISR.
Did I make some obvious mistake? If you have any suggestions, I'd be happy.

Regards, Nicolas