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RTOS/66AK2G02: Booting without help of CCS(standalone boot) or SD card boot.

Part Number: 66AK2G02

Tool/software: TI-RTOS

We are using K2GEVM(66AK2G02) which is connected to daughter card. As of now we are booting the board by flashing the test_dsp.out and test_arm.out through ccs. We are using "processor_sdk_audio_1_00_00_06". Now I wanted to boot the board in standalone mode, without loading the firmware(test_dsp.out and test_arm.out) every time from CCS. It would be helpful if some one can point me to the pointer to get this done.

  • Yes, you can convert the .out file to bin application. Then use the create-sdcard.sh script to write the prebuilt bootloader & default app on it. After this rename your custom newly converted .out file to app and copy it on the sd card, replacing the old app file.

    Best Regards,
    Yordan
  • I have two .out binaries. Test_arm.out and test_dsp.out. How to convert two .out to single app binary. I am able to run prebuilt binaries GPIO LED blink.
  • As of now I am trying this link "processors.wiki.ti.com/.../Processor_SDK_RTOS_BOOT_K2G". Will update the status in some time.
  • Megharaj,

    You are referring to correct documentation to convert your images to bootable images.  Here is a quick summary from my notes of creating bootable audio application binary:

    Since you are using Processor SDK Audio, let me share some insight into other things that may be required to get your system boot working efficiently:

    • Ensure that the DSP and ARM binaries are not using MSMC region used by K2G SBL. For SBL memory usage refer to  pdk_k2g_x_x_x\packages\ti\boot\sbl\soc\k2g
    • Performance audio application uses IPC start to synchonize application start between ARM And DSP. You may be required to add a delay prior to IPC attach on the ARM to allow DSP to complete initialization and get ot IPC attach by the time ARM calls this API.
    • We had noticed that ARM and DSP application from performance audio has large heap buffers that add large segments of zeros to the boot image. You can change the BIOS configuration to remove these segments to speed up the boot. (Optional)

    Hope this helps.

    Regards,

    Rahul 

  • Hi Rahul,

    Thank you for the replay. But this dint help. I am not able to boot from sd-card, also from CCS after adding the delay in arm before IPC attach.

    After folowing this link I followed the below procedure.
    ./out2rprc.exe test_arm.out test_arm.rprc
    ./out2rprc.exe test_dsp.out test_dsp.rprc
    ./MulticoreImageGen.exe LE 55 app 0 test_arm.rprc 5 test_dsp.rprc

    I have added delay in test_arm before ipc_attach in systeminit.c as shown below. But it dont help.
    #if 1 // debug: dummy load
    for (k = 0; k < 10000; k++) // Even tried 1 , arm suspends
    {
    tsStart=readTime32();
    pfpBegin(PFP_ID_MAIN,0);
    clkWorkDelay(CLK_WORKCNT_PER_MS); /* This should take about 750,000 cycles to execute, or 750e3/600e6=1.25 msec. */
    pfpEnd(PFP_ID_MAIN,0);
    tsEnd=readTime32();
    }
    delta = tsEnd-tsStart;
    #endif

    This is not working. Console message is showing,

    **** PDK SBL ****
    boot succesfil!

    SD Boot - file open completed successfully.


    If I enable the delay in arm main.c IPC_start(), it will work in CCS, but still does not work in sd card.

    This is my memory configuration

    MEMORY CONFIGURATION

    name                        origin         length        used        unused      attr fill
    ---------------------- -------- --------- -------- -------- ---- --------
    L2SRAM                    00800000 00100000 0008b820 000747e0 RW X
    L1PSRAM                 00e00000 00008000 00000000 00008000 RW X
    L1DSRAM                 00f00000 00008000 00000000 00008000 RW
    SR_MSMC                0c000000 00080000 00080000 00000000 RW
    CORE0_MSMC        0c0c0000 00040000 00029000 00017000 RW X
    SR_0                        80000000 00200000 00200000 00000000 RW
    COMMON_DDR3     80200000 00600000 00001154 005feeac RW
    COMMON2_DDR3   81000000 01000000 01000000 00000000 RW
    SR_DDR3                 82000000 01000000 01000000 00000000 RW
    CORE0_DDR3          86000000 04000000 00931cc3 036ce33d RW X
    DDR3                        8a000000 76000000 00000000 76000000 RW

  • How big is your application image? If the image is too large then I was wondering if you are waiting long enough for image to boot. Did you try to connect to the ARM (without GEL file and see where PC is at).

    We have tried and tested this scenario since start of 2017 and have not had any issues other than the one that I highlighted. We have captured some common debugging steps that may be helpful to debug this setup:
    processors.wiki.ti.com/.../Processor_SDK_RTOS_Boot

    Regards,
    Rahul
  • Hi Rahul,

    Thank you for the response. 

    SBL and app memory was overlapping on on-chip memory.  Moved some app memory contents to DDR3. Everything started working fine.

    Thank you very much for the support.