Other Parts Discussed in Thread: LM10011,
From SPRS691E Figure 7-5 SmartReflex 4-Pin VID Interface Timing - it's not clear when VCNTL 6-bit sequence starts (when VCNTL3 goes low), especially because on ref. designs these open drain pins are connected to pull-ups to VCCIO_18 that can be provided with delay relative to CVDD.
1. Is it started only after VCCIO_18 is applied and VCNTL3 goes high (in other words it waits for pull-ups)?
2. If yes - how long delay between CVDD and VDDIO_18 is allowed (how long CVDD can be kept at 1.1V default start-up voltage)?
3. if not - who initiates 6-bit transfer / VCNTL3 falling edge (for example to LM10011 )? Is VCCIO must be supplied before CVDD because of pull-ups?