Tool/software: TI-RTOS
Hello,
I am trying to run McASP1 on the K2G as a receiver only. I have a clock going to the RX clock and frame sync, but no connection to the TX clock lines. I've made significant progress on this, but I'm not seeing any repeated traffic on the port. My application is based upon the McASP example projects.
I also have McASP0 set up passing audio without issue. The hope is to run McASP0 with 4 serializers in RX, 12 in TX, and McASP1 with 8 serializers in RX for a total of 12 input pins and 12 output pins.
In order to run the McASP RX State machine off of the RX clock pins, I had to set the ASYNC bit (which is located in the TX State machine registers). In order to set the ASYNC bit, I had to start up the TX state machine. In order to start the TX state machine, I had to set up an extra serializer as TX and set up the TX clocks using the internal clock. In order to prevent TX underrun, I had to delete the TX channel before I start the transfers. So, now everything compiles and starts up. The LPSCs are on, the clocks are running, and I'm just curious what else I might need to check.
It's worth noting that I have Linux running on the other core. I have set aside the EDMA channels in the device tree, but I am not confident in my setup on the DSP end for the DMA. I have the structures to reserve the channels, but I am not sure what shadow region corresponds to which core. So it's possible that the callback is not getting called because the EDMA event is not making it through. I'll be looking into that next week, but I just thought I'd ask you all to see if anyone had any ideas (or knows if this is even possible).
Cheers,
Jeff
