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RTOS/TMS320C6657: SPI NOR boot failure from SPI CS1 (SPISCS1)

Wondong Kim
Prodigy 40 points
Part Number: TMS320C6657

Tool/software: TI-RTOS

Dear All,

I designed custom board using TMS320C6657. And I succeed to boot with test code image (GPIO LED test code) from SPI NOR Flash with DDR initialization.

I connected SPI NOR Flash to SPISCS0 (SPI CS0). 

When I succeed to boot, I set "csel = 2" in nysh.spi.map, and set boot mode pin BOOTMODE [8:7] to "10".

I succeed to boot and I have a correct SPI CS0 pin interface.

I followed SPIboot_with_DDR_UserGuide from below link.

http://processors.wiki.ti.com/index.php/KeystoneI_Bootloader_Resources_and_FAQ#Direct_Boot_Examples_.28without_IBL.29

But I change SPI NOR chip select signal from SPISCS0 (SPI CS0) to SPISCS1 (SPI CS1).  

Also I modifies nysh.spi.map like below and re-run spiboot.bat: 

section {

...

csel = 1 /* for SPI CS1 */

...

}

And I set boot mode pin BOOTMODE [8:7] to "01". But there is no SPI CS1 after power on or reset.

Isn't it possible to boot from SPI CS1?

Thank you and best regards.

  • 0
    TI__Guru**** 161600 points
    Hi,

    I've notified the RTOS team. They will post their feedback directly here.

    Can you share which TI RTOS SDK version are you using?

    Best Regards,
    Yordan
  • 0
    TI__Guru* 81335 points
    After the configuration, are you seeing any of the CS go from high to low ? The place to check would be the boot parameter table populated by the boot ROM, do we know what the ROM sets up in that boot parameter structure?

    Thank you.
  • 0 in reply to Yordan Kovachev
    Prodigy 40 points
    Hi,

    I use TI RTOS SDK 4.03.00.05 and PDK C6657 2.0.9.

    Best Regards,

    Wondong KIM.
  • 0 in reply to Raja
    Prodigy 40 points

    Hi, Raja,

    SPI CS1 is stucked at high but SPI CS0 goes from high to low.

    Below is boot parameter table for SPI CS0. It shows 0x0002 at 0x12 address for SPI CS0.

    1651 1 10000 1 663c
    0x00500000
    0x00320000
    0x40130002
    0x00010018
    0x00040002
    0x00020000
    0x03e80000
    0x01f40000
    0x04000000
    0x00000000

    And, BOOT MODE pin for SPI NOR CS0 boot is like below:

    BOOT MODE12 ..... BOOT MODE0

    1 0 0 1 1 0 0 0 0 0 1 1 0

    Below is boot parameter table for SPI CS1. It shows 0x0001 at 0x12 address for SPI CS1.

    1651 1 10000 1 663c
    0x00500000
    0x00320000
    0x40130002
    0x00010018
    0x00040001
    0x00020000
    0x03e80000
    0x01f40000
    0x04000000
    0x00000000

    And, BOOT MODE pin for SPI NOR CS1 boot is like below:

    BOOT MODE12 ..... BOOT MODE0

    1 0 0 1 0 1 0 0 0 0 1 1 0

    The others like boot image and PLL settings are same for CS1 and CS0.

    Also I checked with other two of our custom board and I have same issue.

    Best regards

    Wondong KIM

  • 0 in reply to Wondong Kim
    TI__Guru* 81335 points

    It should be byte 18(chipsel) not byte 12 in boot parameter table.

    18 Chipsel The chip select used (valid in 4-pin mode only). Can be 0-3.

    Please refer the document in C6657_directROM_Boot_example from below link,

  • 0 in reply to Raja
    Prodigy 40 points
    Hi,

    Chipsel location in boot table is 18 (decimal). In my comment, I use hex decimal number 0x12H that is 18 in decimal.

    My point is why there is no SPI CS1 for boot.

    I succeeded to SPI NOR flash boot with SPI CS0. In this case, SPI CS0 changes from '1' to '0' and '0' to '1'.

    But I just change to SPI CS1, and I have no SPI CS1 signal.
    SPI CS1 is stuck at '1' although SPI CLK and SPI MOSI change '1' to '0' and '0' to '1' in same manner when I boot using CS0.

    In addition, I already followed your reference example.

    Thank you.

    Wondong KIM.
  • 0 in reply to Wondong Kim
    TI__Guru* 81335 points
    Hi,

    There is seems to be issue with ROM bootloader source on CS1. Only during the spi transfer, the SPI CS has been used.

    Please refer the functions hwSpiConfig() and hw_spi_xfer() of spi.c
    ROM bootloader source:
    processors.wiki.ti.com/.../Keystone_Device_Architecture

    We are working with ROM bootloader author to confirm this and raise the ticket . Upon confirmation, the errata will be updated.

    Thank you.