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66AK2L06: Why the clock rate of the DEF must be: 122.88/245.76 or 368.64 Mhz?

user4471589
Prodigy 10 points
Part Number: 66AK2L06
Other Parts Discussed in Thread: ADC32RF42,

Hello:

Why the clock rate of the DEF  must be: 122.88/245.76 or 368.64 Mhz? 

 if  I use adc32rf42 to sampling a GPS signal, I want to make the  sampling rate of is 741 Mhz, How can I set clock rate of the DEF ? And the clock rate of  JESD20B is what?

thinkyou!

  • 0
    TI__Mastermind 37500 points

    Hello,

    The 66AK2L06 DFE section, has a PLL which allows for a 122.88Mhz input and a 245.76 or 368.64Mhz DFE clock.   There is a special multiplier divider arrangement both the for the DFE and IQN clocks, and for the JESD SYSClock sampled at 122.88Mhz.  The clock rate and DFE IQ processing rates have a set of selected ratios.

    Please see the "  www.ti.com/.../spruhx8a.pdf"   Keystone 2 DFE User Guide  for more details.

    The highest close multiple is 368.64Msps.

    Regards,

    Joe Quintal