Hi,
We are using a TMS320C6678 DSP connected by SRIO (Port 2 only) to a Kintex Ultrascale FGPA. The link is configured as 1x @5.0Gb/s.
SRIO reference clock to DSP and SRIO reference clock to FPGA are coming from the same clock source.
We want to test (and tune) our SRIO Link with PRBS7 patterns transmitted between the FPGA and DSP. Our FPGA is able to transmit PRBS7 through its Tx port and verify PRBS7 data on its Rx Port. (IBERT design type).
On the other side, our concern is how to activate the DSP ‘PRBS7 features that seem to exist both at DSP’ Rx side and DSP’ Tx side
For example we have initialized @(0x02620374) = 0x04440485, and @(0x02620378) = 0x001E8015 in order to define the testpattern as ‘PRBS7’
In that configuration the FPGA recognizes the pattern without any error.
But on the DSP side , it is not clear which register/bit to look at.
We observed the SRIO_SERDES_STS register (0x02620154).bit15 but it is not stable : OK for 1 second, then NOK for 1 second, and so on…
At the contrary if we switch the FPGA TX pattern to another PRBS type, then SRIO_SERDES_STS.bit15 remains stable NOK.
Hence the questions:
- Are the above register initialization enough for our test ?
- Then, how to correctly configure the DSP RX side to check/verify PRBS patterns ? What are the register involved here ?
- Which REGISTER.bit gives the OK/NOK result ?
Nota : We also tried to configure the DSP in loopback mode using @(0x0291 B180).bit23 = 1, but as explained in the Errata Advisory 17, the link is not stable and some data are corrupted
Thank you for your help,
Regards,
Yohann
