Tool/software: TI-RTOS
Perusing pdk_k2g_1_0_9, there is a lot of source that is irrelevant to the K2G processor and gets preprocessed out. However, there is also some code that does get compiled that seems unrelated. In particular, pdk_k2g_1_0_9/packages/ti/csl/csl_cacheAux.h CACHE_invL1d et al contain several workarounds-- disabling interrupts for the duration of the invalidation, explicit invalidation of the prefetch buffer, a second mfence operation-- with little description other than "advisory 6". There is no advisory 6 in the K2G errata. I found no advisory 6 on ti.com, but I did find advisories 9 and 13 for the C665x which matches the workarounds.
Please clarify-- are these workarounds are unnecessary for the K2G (ie, should they have been guarded by preprocessor conditions)?
Are there other workarounds in the K2G PDK that are unnecessary on the K2G?
Thank you