RTOS/66AK2H14: EMIF address shifting

Hi Mahina,

Can I get a few clarifications? Your code includes the comment /* 8-bit flash */. Are you connecting to an 8bit device or a 16bit device? Are you configuring the EMIF for x16bit operation?  The logic analyzer capture is showing the addresses as CP_EMIF16_A[23..0]. Are the lines connected to the EMIF signals on the K2H based on those signal names? In other words, is CP_EMIF16_A0 connected to EMIFA00 on pin F34? 

You were speculating on the rotation of the addresses. As specified in the EMIF16 users guide, the signal for the least significant address will appear on EMIFA23 in x16bit mode. That is why you have to connect EMIFA23 to the A0 line on your memory device. EMIFA0 would be connected to A1 on your memory device, etc. The K2H does not internally shift the addresses to support the memory bus width you have selected.

Regards, Bill

Hi Bill,

Thank you for your suggestion. I am able to read/write to CPLD.

I have another question,

We have to achieve maximum throughput , for that I reduced the setup , strobe, hold cycles to 1,5,1 respectively.

I am able to read/write with above configuration.

When I signal tap the read operation I can see delay between 2 read and it is taking nearly  23 cycle for another read.

I have attached the screen shot for your reference.

I am reading 4096 locations and my read function is

 static uint32_t cpldReadDataBytes()
 {
     uint16_t  *data_addr;
     uint16_t i=0;

     data_addr = (uint16_t *)CPLD_DATA_ADDR;

     while(i<SIZE)
     {

         pBuffer[i++]=*data_addr++;
     }
     return 0;
 }

Q1. Why that delay is incured?How to reduce that delay ?

Thanks and Regards,

Mahima Shanbag

Hi Mahima,

The EMIF16 was not designed for streaming data into or out of the device but there are some changes to the method of data transfer that will reduce the delay. The code you've included must initiate a transfer within the EMIF16 for each access to the memory and there is a delay associate with that setup and with the code to perform the while loop. In which memory area is pBuffer located? There is also a delay associated with taking the data read from the EMIF and writing it to pBuffer. A better method is to use a EDMA transfer to access the EMIF16 internally using consecutive 32bit reads. The EMIF16 will break the 32bit accesses into two individual 16bit external accesses. The EMIF16 is the same as the one used on previous KeyStone parts. The links below have some very good information on optimizing the data transfer.

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/192245?tisearch=e2e-quicksearch&keymatch=emif%20throughput#pi316458=1

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/339211

Regards, Bill