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XEVMK2LX: Maximum supported ADC data rate

Majid Boloorian
Prodigy 220 points
Part Number: XEVMK2LX
Other Parts Discussed in Thread: 66AK2L06, RFSDK, DAC37J82, DAC38J84, ADC32RF80

I am trying to calculate the maximum ADC rate that can be supported by the 66AK2L06 EVM on each FMC connector. Are the following calculations correct?

  • Each FMC connector has 2Rx JESD204B lanes each at 7.37Gbps. This is an aggregate line rate of 14.74Gbps. With 8b10b coding this implies true data rate of 14.74*8/10=11.8Gbps
  • So maximum supported ADC sample rate for 10-16bit ADCs is 11.8/16 = 737MSPS. Or should I divide by the ADC resolution in this last calculation, how is the data packed?
  • 0
    TI__Mastermind 37500 points
    Hello,
    The first FMC connector has all 4 JESD 204B lanes. The second FMC connector has a switched version of JESD lanes 2 and 3.
    The serdes portion is capable of 7.3728Gbps per lane. The JESD 204 talks about 10bits by 8bdata. In the K2L this is 20 bits for 16bits of 2s complement data, where the MSB is the sign bit.

    See the RFSDK link for a description of the ARM software that controls the 66AK2L06, TCI6630K2L. "http://www.ti.com/tool/rfsdk"

    While the ADC has an interface at that rate, it has to also match the internal DFE architecture. There is a TIDEP, that discusses 1 or 2 receiver - ADC- JESD interfaces "www.ti.com/.../tidep0081".

    Please review the DFE User Guide. "www.ti.com/.../spruhx8a.pdf"

    1 real ADC with special 2 JESD lane format. not HD mode. 737.28Msps, 7.3728Gbps
    1 complex Receiver stream with an RF ADC and digital receiver, 2 JESD lane format, 368.64Msps IF sampling, 7.3728Gbps
    2 complex Receiver stream with an RF ADC and digital receiver, 4 JESD lane format, 184.32Msps IF sampling, 3.6864Gbps

    At the Rx baseband side of DFE that goes to IQN2 the stream rate is reduced to a channel rate.
    1 complex baseband - 122.88e6 IQ rate
    2 complex baseband - 92.16e6 IQ rate
    4 complex baseband - 30.72e6 (46.08e6 possible but not currently supported) IQ rate

    Regards,
    Joe Quintal
  • 0 in reply to Radio-Joe
    Prodigy 220 points
    Hi Joe

    Thanks for the fast response. I notice that using the DFE will limit the throughput. In our application we do not necessarily need the DFE functionality. We would like to get raw data into the DSP (in a ping-pong buffer in memory) as fast as possible. We need a time synchronized dual ADC configuration (similar to IQ receiver).

    What is the maximum dual ADC sample rate (12-14bit resolution) that can be used with the 66AK2L06 EVM. From the information provided it appears that we should be able to use all 4 Rx JESD lanes on the first FMC connector and get 737.28Msps per ADC channel in dual channel configuration. Is this correct? Is there a subsequent speed limitation at the IQN2 that will prevent this?

    We also need a DAC in our system to be driven from the 66AK2L06 EVM. The DAC identified is DAC37J82. Can the DAC EVM be driven from the other FMC connector or do we need the deterministic latency card to get the DAC and ADC better synchronized?

    Thank you.
  • 0 in reply to Majid Boloorian
    TI__Mastermind 37500 points
    Hello,
    There is no wideband bypass from the JESD Serdes / JESD block to the IQN2 Baseband interface.
    While the JESD-serdes can process data this quickly, the DFE signal processing, and IQN2 baseband interfaces can not.

    The widest 2 Rx streams - 2 Baseband channels. is 184.32Msps stream complex input -> mix/filter/dec2 -> 92.16Msps complex output.
    Input bus to Rx Signal Processing is interleaved at DFEclk/numRxstreams.
    Output bus from Rx Signal Processing is interleaved at DFEclk/(numRx streams * 2)

    The widest 2 Tx stream - 2 baseband channels is 92.16Msps complex input -> 184.32Msps complex output for loopback or DAC
    368.64Msps complex output to DAC.

    There is a TIDEP-0081 "www.ti.com/.../tidep0081 " design using the ADC32RF80, DAC38J84 .

    The Deterministic Latency card, really splits the JESD lanes, clocks, SPI/GPIO and SYNC signals into the two sets one for DAC one set for ADC,
    and provides a 122.88Mhz clock. You could make a passive board/cable for the JESD / SPI /GPIO portions.

    You should contact the third party provider Azcom LTD for the Deterministic Latency card, or fabricate one, they are not stocked/sold by Texas Instruments.

    Regards,
    Joe Quintal