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66AK2G12: Input capacitance ?

Naoki Kawada
Guru 19890 points
Part Number: 66AK2G12

Hi,

My customer wants to know Input capacitance information for 66AK2G12 pins. I checked the datasheet, but i could not find the spec. Do you have any suggestions ?

Best Regards,
NK

  • 0
    TI__Mastermind 42545 points

    Hi NK,

    I'm not sure what you are asking for.  Are you trying to define the bypass capacitance needed for the power delivery network?

    Regards, Bill

  • 0 in reply to Bill Taboada
    Guru 19890 points
    Hi, Bill

    Thanks for your reply. My customer is considering to use a buffer to distribute clocks to K2G and other system parts. In the perspective of fanout, it seems like they would like to know the input capacitance for IO pins of K2G. Does it answer to your question ?

    Best Regards,
    NK
  • 0 in reply to Naoki Kawada
    TI__Mastermind 42545 points

    Hi NK,

    Based on your question it sounds like you are planning on driving multiple clock inputs with a single buffer. I would recommend you avoid this. Reflections on clock signals can cause noise on the clock input to the device creating false edges and, possibly, false clock inputs into your part. I strongly suggest you drive each clock with it's own buffer. Clock distribution parts are available that will keep these clock edges close.

    Regards, Bill

  • 0 in reply to Bill Taboada
    Guru 19890 points
    Hi, Bill

    The customer understands your point, but the clock frequency is not so high, so they are considering that it would be okay to distribute the clock from a single buffer to system parts. Could you please suggest the information of input capacitance ?

    Best Regards,
    NK
  • 0 in reply to Naoki Kawada
    TI__Mastermind 42545 points
    Hi NK,
    The LJCB clock inputs used in the K2G are designed to provide a very clean, low jitter clock to the internal clocking circuit of the device. The expectation is that the clock input to the device will be differential and will be point-to-point. The clock frequency may be slow but the edge rates are not. Chaining a signal clock buffer to multiple clock inputs will add reflections and violate the clocking requirements at the input. I suggest the customer include an LVDS clock fanout buffer such as the SN65LVDS10x.
    Regards, Bill
  • 0 in reply to Bill Taboada
    Guru 19890 points
    Hi Bill, I think what they are asking is not for differential clocks, but for generic IO , such like McASP audio clock (for AHCLKx, ACLKx and AFSx) or something. Best Regards NK
  • 0 in reply to Naoki Kawada
    TI__Mastermind 42545 points

    Hi NK,

    Those clocks use standard LVCMOS buffers. The load capacitance is 4pF.

    Regards, Bill

  • 0 in reply to Bill Taboada
    Guru 19890 points
    Hi Bill,
    Thanks for your clarification. I'll suggest the same to the customer. I think that answers to their question.

    Best Regards,
    NK