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CCS/TMS320C6678: 6678EVM spi boot DDR configuration parameter Boot Parameter

qiang li
Prodigy 30 points
Part Number: TMS320C6678

Tool/software: Code Composer Studio

TI engineer：

   

Hello!

       6678EVM spi boot The official routine has been successful. I have encountered several problems in the reference parameter configuration when referring to the provided parameters. I have already marked it in red. Please answer it.

       The purpose is to make the parameter configuration  understand, so that we can quickly configure the load startup parameters when we use 6678 to make  own version.

1. The Boot Parameter parameter file is located in i2crom.ccs. The related parameters are as follows:

0x 0050 0000 //length: What is the basis for the length of 80 bytes? &checksum:0

0x 0032 0000 //SPI bootmode: 50&portnum:0

0x 4013 0002 //swPllCfg_msw&/swPllCfg_lsw,see PLL Configuration table,cpu :100*19/2=950, check the manual 100M input, 1000M output PLLD should be 0, PLLM should be 19, how to explain?

0x 0001 0018 //options:1&addrWidth:24

0x 0004 0000 //npin:4&chipsel:0

0x 0001 0000 //mode:1&c2Delay

0x 03e8 0000 //cupFreqMhz: 1000MHZ&busFreqMhz:0

0x 01f4 0000 //bhsFreqKhz:500K bus rate&readaddrMsw:0

0x 0400 0000 //read address is 0x00000400, which is 1Kbytes place &next_csel

0x 0000 0000 //next_Read _addr_msw&next_Read _addr_lsw

2. The DDR configuration parameter is located in AddDDrTable. The relevant parameters are as follows:

0x 00 00 00 70 //4 bytes per parameter, 28 parameters, 112 bytes, so that the interpretation is correct?

0x 00 87 35 00 // DDR table start address

0x 02 42 80 F5 //config select: the basis for not finding the parameter?

0x 00 00 00 00 //pll Prediv:0 prediv 0 is disable the pll, can the board be assigned 0 afterwards?

0x 00 00 00 1C //pll Mul: 28

0x 00 00 00 02 //pll post div: 2 DDR input clock is 66.7MHz, 66.7*28/2=933.8, and DDR clock is 1333, not quite right

0x 63 06 2A 32 //sdram config

0x 00 00 00 00 //sdram config2 are all configured as 0?

0x 00 00 14 50 //sdram fresh cntrl, provided in DDR register calc is 0x 00 00 14 58?

0x 11 13 78 3C //sdram timing1

0x 30 71 7F E3 //sdram timing2

0x 55 9F 86 AF //sdram timing3

0x 00 00 00 00 //lpDdrNvmTiming

0x 00 00 00 00 // powerManageCtl

0x 00 00 00 00 //iODFTTestLogic

0x 00 01 00 00 //perform count config, can not find the parameter basis

0x 00 00 00 00 //performCountMstRegSel

0x 00 00 00 00 //readIdleCtl

0x 00 00 00 00 //sysVbusmIntEnSet

0x 70 07 32 14 //sdRamOutImpdedCalCfg, can not find the parameter basis

0x 00 00 00 00 //tempAlterCfg

0x 00 10 01 0F // ddrPhyCtl1, can not find the parameter basis

0x 00 00 00 00 //ddrPhyCtl2; are all coordination 0?

0x 00 00 00 00 //priClassSvceMap;

0x 00 00 00 00 //mstId2ClsSvce1Map;

0x 00 00 00 00 //mstId2ClsSvce2Map;

0x 10 00 00 00 //eccCtl,, can not find the parameter basis

0x 00 00 00 00 //eccRange1;

0x 00 00 00 00 //eccRange2;

0x 00 00 03 05 //rdWrtExcThresh, no parameter basis found

  • 0
    TI__Guru 65405 points
    Hi Qiang Li,

    The team is notified. They will post their feedback directly here.

    BR
    Tsvetolin Shulev
  • 0
    TI__Guru* 81335 points

    Hi Qiang,

    Please refer the Section 2.5.3 Boot Parameter Table of data manual for your understanding.

    Thank you.

  • 0 in reply to Raja
    Prodigy 30 points
    Hi Raja,
    I have read the relevant documents. The values of these parameters marked in red are given by the official routine. There is no problem in verifying the EVM6678 development board. I can't explain the problem according to the problem (I understand the parameter value. In the note), please explain your explanation.
  • 0 in reply to qiang li
    TI__Guru* 81335 points

    1. The Boot Parameter parameter file is located in i2crom.ccs. The related parameters are as follows:

    0x 0050 0000 //length: What is the basis for the length of 80 bytes? &checksum:0

    0x 0032 0000 //SPI bootmode: 50&portnum:0

    0x 4013 0002 //swPllCfg_msw&/swPllCfg_lsw,see PLL Configuration table,cpu :100*19/2=950, check the manual 100M input, 1000M output PLLD should be 0, PLLM should be 19, how to explain?

    0x 0001 0018 //options:1&addrWidth:24

    0x 0004 0000 //npin:4&chipsel:0

    0x 0001 0000 //mode:1&c2Delay

    0x 03e8 0000 //cupFreqMhz: 1000MHZ&busFreqMhz:0

    0x 01f4 0000 //bhsFreqKhz:500K bus rate&readaddrMsw:0

    0x 0400 0000 //read address is 0x00000400, which is 1Kbytes place &next_csel

    0x 0000 0000 //next_Read _addr_msw&next_Read _addr_lsw



    I just checked rom bootloader source code for length, its not been used. You can just use the same value. The i2crom.ccs file is generated from the romparse utility based on the input provided by .map file.

    section {
    boot_mode = 50
    param_index = 0
    options = 1
    core_freq_mhz = 1000
    exe_file = "spiboot.i2c.ccs"
    next_dev_addr_ext = 0x0
    sw_pll_prediv = 5
    sw_pll_mult = 32
    sw_pll_postdiv = 2
    sw_pll_flags = 1
    addr_width = 24
    n_pins = 4
    csel = 0
    mode = 0
    c2t_delay = 0
    bus_freq_mhz = 0
    bus_freq_khz = 500
    }


    Please refer the map file in the example provided,
    processors.wiki.ti.com/.../File:C6678_directROM_boot_examples.zip

  • 0 in reply to Raja
    TI__Guru* 81335 points

    Also note, the DDR configuration table for C6678 doesn`t contain DDR levelling configuration and the DDR initialization sequence has changed slightly since the last revision of the RBL so it is recommended that you run the DDR at lower speeds while initializing it from the RBL and then speed it up  from the application initialization code.

    Please refer this thread for DDR init,

    Thank you.

  • 0 in reply to Raja
    Prodigy 30 points
    Hi Raja,
    You provided sw_pll_prediv = 5、sw_pll_mult = 32、sw_pll_postdiv = 2 in .map file. Input clock 100MHZ, calculate the system clock according to the parameter is 100/5*32/2=320MHZ, is this calculated correctly? Why should I configure it like this, I understand that it is configured to 1000MHZ, is it suitable for less than the maximum support frequency?

    DDR initialization table performance does not need to be configured? To initialize DDR in the program? In this way, data cannot be moved from FLASHB to DDR at boot time, and can only be moved to other memory modules. After the program is run and DDR is initialized, DDR can be used. Is this correct?

    In addition, please explain my red labeling parameters. I did not find the parameters in the relevant documents.
  • 0 in reply to qiang li
    TI__Guru* 81335 points

    You provided sw_pll_prediv = 5、sw_pll_mult = 32、sw_pll_postdiv = 2 in .map file. Input clock 100MHZ, calculate the system clock according to the parameter is 100/5*32/2=320MHZ, is this calculated correctly? Why should I configure it like this, I understand that it is configured to 1000MHZ, is it suitable for less than the maximum support frequency?



    Yes, your calculation is correct. The ROM boot loader does use only the PLL configuration values(sw_pll_xxxx) from boot parameter table and not the "core_freq_mhz". There is no impact on "core_freq_mhz" from boot parameter table that is passed.

    DDR initialization table performance does not need to be configured? To initialize DDR in the program? In this way, data cannot be moved from FLASHB to DDR at boot time, and can only be moved to other memory modules. After the program is run and DDR is initialized, DDR can be used. Is this correct?


    Yes, your understanding is correct.

    Thank you.