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66AK2H14: SRIO Serdes default configuration register defines and register base address + offsets

Joe Freeman94
Prodigy 170 points
Part Number: 66AK2H14

I'm developing a SRIO driver for VxWorks7.

Referencing:

SerDes_spruho3a.pdf:

TI requires customers to use TI-generated and supported, default PHY configurations for all
operating modes (supplied as part of MCSDK). TI cannot directly support customer
generated configuration files. The code/registers used and accessed in these configurations
must be considered as the "default" for a given interface use-case and must not be modified
by a customer.

Referencing:

https://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/501793

I found the default SRIO Serdes configuration file for a 5Gbps line rate. Where do I get default SRIO serdes configuration for the RAPID IO line rates of  1.25Gbps, 2.5Gbps  and 3.125Gbps?

File for 5Gbps line rate:

    ..\ti\pdk_k2hk_4_0_10\packages\ti\csl\src\ip\serdes_sb\V0\csl_wiz8_sb_refclk156p25MHz_20bit_5Gbps.c

There are  ~25 configuration magic register undocumented. How do you debug this interface?

SRIO sprugw1b.pdf in the Release History there are references to  Serdes Spec sheet. Where can get the Serdes Spec sheet?

Release History:

    Changed ENRX to ENTX in SRIO_SERDES_CFGTX to match the Serdes Spec sheet.

The SRIO  register base address + offsets for configuration register are not clearly defined. SRIO sprugw1b.pdf reference SRIO config register at absolute addresses. The tci66ak2h14.pdf  defines the SRIO  and SerDes base addresses at a different address. Can I use the lower address bit as an register offset, as defined in sprugw1b.  And append in the tci66ak2h14 base address

Example:

SerDes Receive Channel Configuration Register n (SRIO_SERDES_CFGRX[0-3]) (0x02620364 +(n * 0x8))
SerDes Transmit Channel Configuration Register n (SERDES_CFGTXn_CNTL) (0x02620368 + (n * 0x8))

tci66ak2h14 BASE_SRIO_SERDES_CFG_REGS        (0x0232C000)

SRIO_SERDES_CFGRX[0-3])(0x0232C000 + 0364 +(n * 0x8)

(SERDES_CFGTXn_CNTL) ( 0x0232C000 + 0368 + (n * 0x8))

Does this base address substitution work for all SRIO and Serdes register? Or have the register offset changed ?

Tks,

Joe Freeman

  • 0
    TI__Guru**** 161600 points
    Hi,

    I am looking into this.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    TI__Guru**** 161600 points
    Hi,

    SRIO sprugw1b.pdf in the Release History there are references to Serdes Spec sheet. Where can get the Serdes Spec sheet?

    See:
    www.ti.com/.../sprac37.pdf
    www.ti.com/.../spruho3a.pdf

    Does this base address substitution work for all SRIO and Serdes register? Or have the register offset changed ?

    You can check SRIO and Serdes base addresses from the Datasheet: www.ti.com/.../66ak2h14.pdf See Section 8.1 Memory Map Summary for 66AK2Hxx and Table 8-1. Device Memory Map Summary for 66AK2Hxx.
    SRIO SerDes Config base address: 00 0232 C000
    SRIO Serial Rapid IO configuration: 00 0290 0000

    So the base address 0x0232C000 is only for the SerDes configuration related to SRIO.

    Best Regards,
    Yordan
  • 0
    Prodigy 170 points

    The serdes config offsets from the sprugw1b.pdf  did not work. If I use these offsets and write the srdes config register and then read it back I get  a value of zero.

    Looking at the TI RTOS K2h driver.  This driver uses different serdes offsets. These are not documented in the SRIO sprugw1b.pdf User Reference.

    ..\TI\pdk_keystone2_3_00_03_15\packages\ti\drv\srio\device\k2h\src\device_srio_loopback.c

            /* Disable PLL Before Configuring Serdes Reg */
            *(volatile uint32_t *)(CSL_SRIO_SERDES_CFG_REGS + 0x1ff4) = 0x00000000;

    C:\Storage\TI\pdk_keystone2_3_00_03_15\packages\ti\csl\src\ip\serdes_sb\V0\csl_serdes_srio.h

         *(volatile uint32_t *)(base_addr + 0x1fe0 + 4*lane_num) = 0xF0C0F0F0;

           CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x200*(lane_num+1)),31,24, 0x40);

    These offset seem to work. I can write a value to the register and read back the same value.

    So the big question is,, where are the register offsets for Serdes config register for a TI tci66ak2h14  SOC defined?

    tks,

  • 0 in reply to Yordan Kovachev
    Prodigy 170 points
    That is the base address. What are the register offsets for all the 100+ configuration register?
  • 0 in reply to Joe Freeman94
    TI__Guru**** 161600 points
    Sorry for the confusion.

    The SRIO Serdes Configuration registers are located in the SRIO User Guide: www.ti.com/.../sprugw1b.pdf
    See Section 3.1 SerDes Macro Registers and Section 3.2 SerDes Receive/Transmit Channel Configuration Registers.

    Let me check the Processor SDK RTOS sources to verify that.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Prodigy 170 points
    These absolute address are not correct for the TI tci66ak2h14 SOC.

    Please provide corrected documentation.

    Thanks,
    Joe Freeman

    sprugw1b.pdf:
    SerDes Macro Status Register (SRIO_SERDES_STS — 0x02620154)
    SerDes Macro Configuration Register (SRIO_SERDES_CFGPLL — 0x02620360
    SerDes Receive Channel Configuration Regist
    er n (SRIO_SERDES_CFGRX[0-3]) (0x02620364 +(n * 0x8)
    SerDes Transmit Channel Configuration Reg
    ister n (SERDES_CFGTXn_CNTL) (0x02620368 + (n * 0x8))
  • 0 in reply to Joe Freeman94
    TI__Guru* 95265 points
    Hi,

    Please check: www.ti.com/.../sprac37.pdf section 1

    Those:
    0x02620360 4B SRIO_SERDES_CFGPLL
    0x02620364 4B SRIO_SERDES_CFGRX0
    0x02620368 4B SRIO_SERDES_CFGTX0
    0x0262036C 4B SRIO_SERDES_CFGRX1
    0x02620370 4B SRIO_SERDES_CFGTX1
    0x02620374 4B SRIO_SERDES_CFGRX2
    0x02620378 4B SRIO_SERDES_CFGTX2
    0x0262037C 4B SRIO_SERDES_CFGRX3
    0x02620380 4B SRIO_SERDES_CFGTX3

    are ONLY apply to Keystone I device.

    For K2H, this is Keystone II device and the Serdes is different from Keystone I device. The Serdes lane is configured using ..\ti\pdk_k2hk_4_0_10\packages\ti\csl\src\ip\serdes_sb\V0\csl_wiz8_sb_refclk156p25MHz_20bit_5Gbps.c

    The register base address is: #define CSL_SRIO_SERDES_CFG_REGS (0x0232C000)
    Those offset you mentioned, like 0x1ff4, 0x1fe0 is based on this address.

    Regards, Eric
  • 0 in reply to lding
    Prodigy 170 points

    Eric,

    Thanks, for getting back with me.

    I need to enable/disable, configure for loop back and status the KeystonII SRIO serdes. The csl_wiz8_sb_refclk156p25MHz_20bit_5Gbps.c magic WIZ file will only set the default configuration.  I also need magic WIZ  files for the 1.25, 2.5 and 3.125 Gbps SRIO line rates.

    I need a memory map for the Keystone II SRIO serdes " like "  section 1  sprac37.pdf  Keystone I.  Where is the Memory Map for the Keystone II SRIO serdes?

    Joe

  • 0 in reply to Joe Freeman94
    TI__Guru* 95265 points
    Joe,

    The Serdes of Keystone I and Keystone II are totally different.

    It will be clearer if you look at the below Serdes project created by: "pdkProjectCreate.bat K2H all little serdes_diag all dsp". Then import the CCS project, in the serdes_diag_platform.h, change to #define serdes_diag_test_phy_type TEST_SERDES_SRIO /* Enables SRIO serdes tests */

    Then build the code and you can navigate how the code initialize the serdes part:
    main()--------------->serdes_diag_test_init()---------->
    status = CSL_SrioSerdesInit(serdes_lane_enable_params.base_addr,
    serdes_lane_enable_params.ref_clock,
    serdes_lane_enable_params.linkrate)

    You can see the different clock rate and link rate using different configuration files.

    if (!(ref_clock == CSL_SERDES_REF_CLOCK_125M || ref_clock == CSL_SERDES_REF_CLOCK_156p25M || ref_clock == CSL_SERDES_REF_CLOCK_312p5M))
    {
    return CSL_SERDES_INVALID_REF_CLOCK;
    }
    if (ref_clock == CSL_SERDES_REF_CLOCK_125M && rate == CSL_SERDES_LINK_RATE_5G)
    {
    csl_wiz8_sb_refclk125MHz_20bit_5Gbps(base_addr);
    }
    if (ref_clock == CSL_SERDES_REF_CLOCK_156p25M && rate == CSL_SERDES_LINK_RATE_5G)
    {
    csl_wiz8_sb_refclk156p25MHz_20bit_5Gbps(base_addr);
    }
    if (ref_clock == CSL_SERDES_REF_CLOCK_125M && rate == CSL_SERDES_LINK_RATE_6p25G)
    {
    csl_wiz8_sb_refclk125MHz_20bit_6p25Gbps(base_addr);
    }
    if (ref_clock == CSL_SERDES_REF_CLOCK_156p25M && rate == CSL_SERDES_LINK_RATE_6p25G)
    {
    csl_wiz8_sb_refclk156p25MHz_20bit_6p25Gbps(base_addr);
    }
    if (ref_clock == CSL_SERDES_REF_CLOCK_312p5M && rate == CSL_SERDES_LINK_RATE_6p25G)
    {
    csl_wiz8_sb_refclk312p5MHz_20bit_6p25Gbps(base_addr);
    }
    if (!(rate == CSL_SERDES_LINK_RATE_5G || rate == CSL_SERDES_LINK_RATE_6p25G))
    {
    return CSL_SERDES_INVALID_LANE_RATE;
    }
    return CSL_SERDES_NO_ERR;

    There are parameters:

    for(i=0; i< serdes_lane_enable_params.num_lanes; i++)
    {
    serdes_lane_enable_params.lane_ctrl_rate[i] = SERDES_DIAG_TEST_LANE_RATE;
    serdes_lane_enable_params.loopback_mode[i] = SERDES_DIAG_TEST_LOOPBACK_MODE;
    ........................


    #define SERDES_DIAG_TEST_LANE_RATE CSL_SERDES_LANE_FULL_RATE
    #define SERDES_DIAG_TEST_LOOPBACK_MODE CSL_SERDES_LOOPBACK_DISABLED

    typedef enum
    {
    CSL_SERDES_LANE_FULL_RATE = 0,
    CSL_SERDES_LANE_HALF_RATE = 1,
    CSL_SERDES_LANE_QUARTER_RATE = 2
    } CSL_SERDES_LANE_CTRL_RATE;

    typedef enum
    {
    CSL_SERDES_LOOPBACK_ENABLED = 0,
    CSL_SERDES_LOOPBACK_DISABLED = 1
    } CSL_SERDES_LOOPBACK;

    to determine the lane rate and loopback or not.

    So, 1.25Gbps is quarter rate of 5Gbps, 2.5Gbps is half rate of 5Gbps, 3.125Gbps is half rate of 6.25Gbps. You only have two Serdes configuration files, one for 5Gbps, the other is 6.25Gbps, but relying on 1/4 or 1/2 lane rate to get your desired rate.

    Regards, Eric
  • 0 in reply to lding
    Prodigy 170 points
    Eric,

    I have spent many hours looking at this code trying to understand how the Keystone II SRIO SerDes Register work. I should not have to reverse engineer a code base with 1,000s of lines of code. TI should have a document defining the Keystone II SRIO SerDes registers and their offsets. As they do for all the other devices on this SOC.

    I now have to explain to my customer why I have spent 100s of hours $$ and do not have a working SRIO driver.

    Please provide a document with a memory map defining for Keystone II SRIO SerDes registers and there offsets.

    Thanks,
    Joe Freeman
    Contract Engineer
    919 656 0320
  • 0 in reply to Joe Freeman94
    TI__Guru* 95265 points
    Hi,

    Yes, this document is: www.ti.com/.../spruho3a.pdf. Those registers and offsets applies to all the high speed interface, like PCIE, Hyperlink, XGE, SRIO, etc.

    For SRIO, it is PHY-A four lane: 16.2 Memory Mapping for PHY-A 4 Lane Sub-Systems

    The base address of SRIO is CSL_SRIO_SERDES_CFG_REGS (0x0232C000).

    Regards, Eric
  • 0 in reply to Joe Freeman94
    Prodigy 170 points
    Eric,

    I finally connected the dots. www.ti.com/.../sprac37.pdf defines the the Keystone II Serdes registers and there offsets for the SRIO Type-A 4 lane Serdes. These SRIO Serdes register offsets match the code for TI RTOS reference design.

    Tks,
    Joe