C6000 Multicore DSP

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C6000 Multicore DSP

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6670 multicore boot
Related Posts

  • Forum Post: 6670 multicore boot

    Nick Carter
    Hi all, I'm working on 6670 boot. I wanna boot all four cores. I've succeeded in booting one core from EEPROM via i2c. Now I wanna put the whole booting program in flash. And boot from flash via SPI. But I don't know how to write the booting program. Is it true that each core has a...
    on Apr 20, 2012

  • Forum Post: RE: problem in using MAD tools

    Amandeep Singh
    but when i use " /ccsv5/tools/compiler/c6000/include" path now i am gettin the following error: cl6x -c --abi=elfabi -g --mem_model:data=far -fr=obj -I "C:/Program Files/Texas Instruments/ccsv5/tools/compiler/c6000/include"/include -I../src ../src/printf.c --output_file obj/printf...
    on May 23, 2012

  • Forum Post: problem in using MAD tools

    Amandeep Singh
    Hi i am using C6670 DSP and i want to download the different applications to different cores. i am using MAD tools for this according to the procedure given on http://processors.wiki.ti.com/index.php/MAD_Utils_User_Guide, but when i am invoking the build script( ./build_examples_lnx.sh c6670 little...
    on May 22, 2012

  • Forum Post: Run Program in 6670 Multicore DSP

    Anugerah Firdauzi
    Hello, I'm just started using DSP 6670. In file Bios Multicore SDK 2.0 User Guide, there are some example to create and run simple program. I've tried to do and run Example 2 - Building and running your first tasking application using MCSDK and BIOS in page 46 succesfully. My question is...
    on Jun 12, 2012

  • Forum Post: Mass production with TI development tools

    Angela Mu��oz
    Hi, I want to know if there is any cost for using the DSPLIB and the others tools provided by Texas Instruments to develop applications (like Sys/BIOS, Mathlib, etc.) in a mass production product and what kind of things do an enterprise have to take into account to use them without legal issues. ...
    on Jul 17, 2012

  • Forum Post: Are EDMA CC IPR writes atomic?

    Manu Bansal
    Hi, I'm wondering if updates to the EDMA controller's Interrupt Pending Registers (IPR, IPRH) are atomic. I want multiple DSP cores to post EDMA transfers and poll the interrupt pending register. Upon completion, respective cores will clear respective IPR bits by writing 1 with the appropriate...
    on Jul 23, 2012

  • Forum Post: RE: question about hyperlink interface

    ahmed abouzaid
    any body help me there ??
    on Aug 4, 2012

  • Forum Post: Cannot open FFTC Tx channel

    Igor Almeida
    I am trying to combine the QMSS Infrastructure Multicore Mode (PDK_INSTALL_PATH/ti/drv/qmss/example/InfrastructureModeMulticore) example code with the FFTC multicore (PDK_INSTALL_PATH/ti/drv/fftc/example/multicore) example code and I am getting a strange error during configuration: [C66xx_1] Error...
    on Jul 26, 2012

  • Forum Post: RE: tms320c6678

    Avinash Neethi1
    (Please visit the site to view this file) Hi Chad, I want to know how to calculate the DQS routed length and clock routed length from the PCB length. there are two values in that is DQS and DQS# , In the clock we have two values for P and N value. How to calculate the values from this excel sheet.I...
    on Aug 30, 2012

  • Forum Post: Steps for simulation in tms320c6670

    denzil fernandes
    Hello all, I am new to TI processor i just wanted to know if it is possible to simulate hardware accelerators (like BCP, FFT module). If it please could guide me how to do it or share any document which could help me. Thankyou, Regards. Denzil.
    on Aug 29, 2012

  • Forum Post: EVM Initialization

    Praveen Kumar Janakiraman
    Hi TI, I am using C6670 multicore dsp. I want to know whether it is possible to do EVM initialization in core 1,If i want to use only core 1. Is it a mandatory to use core 0 for initialization in multicore project ? Regards, Praveen Kumar J
    on Jan 22, 2013

  • Forum Post: IPC Not waking/booting other Cores 1-3

    Erick Higa
    We're using a 6670, and running into an issue trying to boot cores 1-3. We can load the code that needs to run on the cores' L2, and set BOOT_MAGIC_ADDRESS to the correct value, however sending the IPC interrupt to the other cores does not seem to start the cores. (The do not seem to start...
    on Jan 9, 2013

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