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AIF2
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  • Forum Post: AIF SerDes Clocking

    YCS
    Hi, I was refering external ref clock for AIF2 PHYSYNC & RADSYNC in literature sprabi2.pdf(Hardware design guide) for CPRI mode,in doc it is mentioned that clock ref should be 307.2MHz(Table16,page91) .Is it should be 245.76MHz or 307.2MHz ?????
    on Jul 21, 2011

  • Forum Post: Re: AIF2 SERDES clocking, PHYsync and RADsync usage.

    Mohamed Khaleel
    Thanks Albert for your quick reply. I have another query with respect to AIF2 clock. From the documentation I could understand that the SYSCLK will be used by the AIF2 module. However in many places in the document it has been mentioned that OBSAI requires 307.2MHz and CPRI requires 245.76 MHz...
    on Jul 25, 2011

  • Forum Post: AIF2 SERDES clocking, PHYsync and RADsync usage.

    Mohamed Khaleel
    For CPRI interface of 6.144Gbps, 1. RP1_CLK and RP1_FB can be left unconnected? 2. Is providing a 10ms accurate pulse on PHYSYNC and RADSYNC is the only requirement? Is this pulse has to be in sync with some other event? -Khaeel
    on Jul 22, 2011

  • Forum Post: Two C6670 communicate with each others through AIF2

    odzy
    Hi all! I am doing a project using the C6670, and here is the problem. I am not familiar with the AIF2. If I want to connect two C6670, what should I do to handle the clock and synchronization? In my oppion, the two DSP can use their own SYSCLKs, and use the same source to drive their RADSYNCs, so...
    on Aug 12, 2011

  • Forum Post: Re: How to measure signal quality of high speed transmission line

    challenger002
    Thank you for an answer. Can I see which measurement equipment was used with an evaluation board of C667x or other boards of C667x which you know? In addition, can I get a test pattern program of C667x DSP which was used with these boards? Thank you.
    on Dec 5, 2011

  • Forum Post: How to measure signal quality of high speed transmission line

    challenger002
    I want to measure signal quality of high speed transmission line. I use sRIO, AIF2, PCIe on C6670 DSP. Which measurement equipments should I use? In addition, is there the example (manufacturer, model number, etc...)? Can you give me DSP software for the measurement? Or is there the information...
    on Nov 24, 2011

  • Forum Post: DESCRIPTOR PUSH SIZE BUG

    RAHUL SHARMA91013
    Hi I am trying to connect directly FFTC and AIF2 module through the Queue 512 ( TX Queue for AIF2) . i get exact output (expected output) on simulator on AIF2 receive queue with length in descriptor field same as we have configured ** so working fine on simulator ** The problem comes when...
    on Dec 21, 2011

  • Forum Post: Re: How to change the values of AIF2 registers

    Krishna Rekhani
    Randy, Well I believe GEL file does that work of powering ON and clocking of AIF2. We are not specifically CSL_PSC_enablePowerDomain (); for AIF2 like we do for FFTC and other peripherals.( I dont know whether we have to do it or not). Well what actually we were trying to see if any AIF2...
    on Jan 6, 2012

  • Forum Post: How to change the values of AIF2 registers

    Krishna Rekhani
    Hi, I need to see the EE registers in AIF2 for any errors(basically the reason why AIF2 is not running). So I am trying to set value of the register(which is at an offset of 0x4004 from the base address of AIF2 by 0x07) . But i cant set these register. I tried by directly changing through the memory...
    on Dec 19, 2011

  • Forum Post: AIF2-CPRI RadT configuration

    Pankaj Kumar
    Hi, We are planning to use AIF2-CPRI configuration for our FDD LTE project. Though we could get example project working if RadClockCountTc is configured with 245759 (1 ms). But we plan to use RadT timer to generate event for every lte ofdm symbol (14 events in one ms). In this case the value of RadT...
    on Jan 9, 2012

  • Forum Post: AIF Question

    demon popo
    Hi, I want to used AIF2 interface on board C6670. I can't find the non-lookback example on CSL file. I wanted to send control message on z.16.0. Can you support the example code? Thank you.
    on Feb 22, 2012

  • Forum Post: AIF2 SYNC reception

    Naoki Takahashi
    Hi, I am having a trouble with AIF2 RM synchronization. What I am trying to do now is to capture the CPRI SYNC symbol in between the window specified by pi_min and pi_max parameters. I'm setting pi_min = 0x0 and pi_max = 0x3E66, which is about the same size as one CPRI hyperframe. Since...
    on Apr 19, 2012

  • Forum Post: C6670 Antenna interface

    Joe Burri
    Hello - I am planning on using a C6670, need to input generic "high-rate" data (20+ Gbit/sec), it's not CPRI/OBSAI. CPRI/OBSAI protocols have a lot of overhead and complexity, are we forced to use CPRI/OBSAI or is there a way to configure the AIF2 to avoid most of the overhead/complexity...
    on Jul 30, 2012

  • Forum Post: PHYSYNC and RADSYNC on TMS320TCI6614

    KevinS
    Hi, I'm currently working in a design using the TMS320TCI6614 and am seeking to know if my understanding of the use of the PHYSYNC and RADSYNC signals for the AIF2 module is correct. I've read the documentation and some forum posts about these signals but still want to make sure we are using...
    on Aug 24, 2012

  • Forum Post: Doubts about AIF2 LLD and the SCBP

    David Martin-Sacristan
    Hi all, In AIF2 LLD User's Guide it is said that the AIF2LLD supports 3 configurations: the Lyrtech EVM, the Advantech board and the Azcom Small Cell Board Platform. Nevertheless I cannot see the project configuration supporting the SCBP in the LTE AIF2 example project of the last PDKs. Besides...
    on Sep 11, 2012

  • Forum Post: Using PI capture to estimate cable length in the AIF2 CPRI interface

    Anuradha Narayanan
    Can you elaborate the procedure to use PI capture to estimate cable length between RE and REC? My understanding is the since PI capture provides the difference in frame offsets between the transmit CPRI frame and the received CPRI frame, it will be the combined delay of transmit and receive paths, plus...
    on Oct 11, 2012

  • Forum Post: AIF2 demo code is not working...

    Swaroop6430
    Hi, I am trying to run the AIF2 demo code which is available in the mdsk19. I am running aif2LteTestProject. I am getting the following error. Would it be posssible to help me out in this. [C66xx_0] Beginning AIF2 LTE CPRI: [C66xx_0] test: CPRI_4X_LTE_20MHZ_2LINK [C66xx_0] AIF CPRI mode [C66xx_0...
    on Jun 11, 2012

  • Forum Post: RE: Antenna Interface AIF2

    RAHUL SHARMA91013
    Hi Albert Thanks for the reply. So it means AIF2 supports the scenario if PD module is catching packets for downlink (loopback mode). Further, what i understand is PD and PE works independently.Is it right? While testing this loop back mode i am sporadically getting a PE error when checking EE...
    on Nov 9, 2012

  • Forum Post: Antenna Interface AIF2

    RAHUL SHARMA91013
    Hi all I have a query regarding AIF2. I am working on EVM 6678. Is AIf2 loopback mode supported in TDD LTE configuration if i have to test through serdes loopback ? BR Rahul
    on Nov 8, 2012

  • Forum Post: AIF2 CPRI Control and Management Channel

    Mehly
    Hi, we try to recieve CPRI C&M from AIF2 with PktDma. Inside of our Test C&M data we use a counter from 0x00 to 0xFF. So normally the Delimiter value 0xFB is omitted. The result is that the Packet length is 1020 Bytes instead of 1024 Bytes (4x CPRI Rate). We tried to configure Packet...
    on Nov 20, 2012

  • Forum Post: connection between TMS320C6670 and Xilinx Spartan FPGA

    Alexander Kuznetsov
    Which interface I can use to make connection between TMS320C6670 and Xilinx Spartan FPGA? I need about 1Gbps rate.
    on Sep 29, 2011

  • Forum Post: Connection between TMS320C6670 and Xilinx FPGA using AIF2

    ANUJ AGARWAL
    Hi I wish to make a connection between 6670 DSP (with respect to each of 4 cores) and FPGA which supports SERDES link. In my case, SRIO is used for inter DSP communication, hence SRIO cannot be used. I am left with option of using AIF2 peripheral, but unable to decide on which feature I can use for...
    on Apr 5, 2013

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