C6000 Multicore DSP

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C6000 Multicore DSP

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  • Forum Post: Re: Hyperlink Specification

    Flemming Christensen
    Dave, Any progress on the formal annoucement? Rgds Flemming
    on Jan 20, 2011

  • Forum Post: Re: 6678 Smart Reflex Supply

    Tom Johnson16214
    The TMDXEVM6678L EVM design for the TMS320C6678 DSP is still in the pre-release phase. Once the design has stabilized, the design collateral including the UCD9222 configuration will be posted for download. Customers receiving early samples should contact their sales FAE for support.
    on Mar 16, 2011

  • Forum Post: TMS320TCI6618 - docs needed for MN and INTC

    Ruslan Senyushkin
    Hi, in http://focus.ti.com/lit/wp/spry161/spry161.pdf whitepaper I see following: For example, Multicore Navigator is able to schedule jobs and instruct the next free DSP core to read a job and process it without the need for external management. This simplifies the SoC’s software architecture...
    on Apr 14, 2011

  • Forum Post: How DSP knows TCP3E&TCP3D Code block processing completion?

    Ashok Kumar78482
    Hi Suppose the DSP ihas sent a set of code blocks of same size to TCP3E for processing,and the DSP need to run next module as each of the code blocks processed by TCP3E instead of waiting to finish processing all code blocks. How CPU can get to know about this event of code block completion. Can...
    on Jul 6, 2011

  • Forum Post: Interrupt info for the C6678

    C. García
    Hi, I have some holes in with the interrupts issue in the C6678 and I hope that the document SPRUGW4 wil help me to solve them. Please, could somebody tell me when it will be available? Please could somebody tell me also if there are additional info besides the item 7-5 in the Data manual...
    on Jun 28, 2011

  • Forum Post: C667x: Running CVDD from a fixed +1.0V supply

    Sara Venhuizen
    We are basing a design on the C667x EVM kit, and recently read the kit errata, which says: "Alpha and Beta1 EVMs operate the CVDD at a fixed voltage and do not use Smart Reflex. A new UCD9222 configuration is needed to enable this. Beta2 EVMs support Smart Reflex. Version 4 of the UCD9222 configuration...
    on Aug 11, 2011

  • Forum Post: SRIO LSU Access in SYS/BIOS

    Simon Locke
    I have the following problem. I have some code which performs a SRIO maintenance read, which executes hapilly before BIOS_start is called. Once BIOS_start is called, the same code is run inside my single thread and the code no longer works. It "completes" in the sense of LSU Reg6 LCB...
    on Oct 27, 2011

  • Forum Post: Re: evmc6678 eithernet speed only 100M

    Raj Sivarajan
    Lucifar, As Jack recommendeds, you should upgrade to the latest version of BIOS-MCSDK, which is R2.0.4 since there are some bug fixes that would affect your results. Here is the User Guide section on product updates (via Eclipse updater within CCS or download page): http://processors.wiki.ti.com...
    on Nov 29, 2011

  • Forum Post: Unused clock pins - Keystone Hardware Design Guide

    Courtney Cooley
    Hello. The Hardware Design Guide for Keystone Devices was recently updated. In the revision history log, the clock termination update is described as "changed pull up location from variable core to fixed core supply." However, when I navigate to the appropriate sections, the content says...
    on Dec 5, 2011

  • Forum Post: C6678 power spread sheet

    one and zero
    Hi Champs, it seems that there is a 'bug' in the excel spreadsheet provided in sprm545. The spreadsheet rev is 1.0.2. The issue I see is the following. Use the default setting of the spreadsheet. The power figures for CVDD1 are: Activity: 13.94 mA Baseline: 1379.62 mA (@1250 MHz)...
    on Jan 10, 2012

  • Forum Post: Help! give me a example of CYCLIC PREFIX REMOVE in FFTC

    Yang Meng
    please give me a example of CYCLIC PREFIX REMOVE in FFTC I have a test , I set Queue Cyclic Prefix Register FFTC_QUEUE_X_CYCLIC_PREFIX_REGISTER = 0x80010000(bit CYCLIC_PREFIX_REMOVE_EN = 1 and bit CYCLIC_PREFIX_REMOVE_OFFSET = 1), the input datas shoud remove the first one(16bit I,16bit Q), but it...
    on Oct 31, 2011

  • Forum Post: Re: How to release lsu shadow registers using prvid ?

    Chaitanaya Chhibbar
    Thanks for your reply, I have tried this, but this is not releasing the shadow registers. Is there any thing else which i need to do with this or does it require some time to release the shadow registers ? eg. privID = gCoreId; CSL_SRIO_CancelLSUTransaction( gSrioHandle, lsuNumber,...
    on Jan 19, 2012

  • Forum Post: How to release lsu shadow registers using prvid ?

    Chaitanaya Chhibbar
    Hi, I am using SRIO peripheral on TI 6618 DSP. The shadow register configuration is set to default i.e. each LSU is using 4 shadow registers. Error Scenario : LSU is locked by one core say core 0 and need to be unlocked using the CBUSY bit. As per the SRIO user guide for the keystone device...
    on Jan 18, 2012

  • Forum Post: Re: Rebuilding image processing demo causes memory range warnings

    Gordon Deane
    Funnily enough, I've just been trying the same thing and am failing to rebuild the image_processing master (although on a 6678) I think I can solve your immediate problem: the image_processing demo uses a custom platform demos.image_processing.ipc.evmc667xl.platform which defines the ranges MSMC_MASTER...
    on Feb 10, 2012

  • Forum Post: EMIF-16 address mapping?

    Gordon Deane
    Another post relating to connecting an FPGA to a C6678 over EMIF-16. The Keystone EMIF docs ( SPRUGZ3A ) show several different ways of configuring the interface, eg. for NAND flash versus NOR flash. We reasoned that our FPGA was most like NOR flash/ASRAM and started working from Fig 2.2 (p2-4) which...
    on Feb 21, 2012

  • Forum Post: Re: TSM320c6670 Boot ROM

    Noryab
    I've reading the KeyStone Architecture SOC Security User Guide (<SPRUHC3>) , the C66x DSP Bootloader User Guide (<SPRUGY5>) , the KeyStone Architecture Bootloader User Guide (<SPRUGY5A>) and the TMS320C6670 Data Manual (<SPRS689C>) . They all briefly mention the two boot modes...
    on Feb 24, 2012

  • Forum Post: DDR3 data transfer overhead!!!

    Mohamed Sohal
    Hi all, We have a data stored in the DDR3 memory. This data is accessed simultaneously by the 8 cores for processing. At this stage there is a possibility of memory read conflicts. How can we reduce this overhead and hence to optimize this memory read/write operations. Regards, Sohal
    on Jan 20, 2012

  • Forum Post: failed to allocate using malloc - 6678

    Mohamed Sohal
    Hi! I am working on 6678 multicore processor. I want to compare the memory overhead caused when data is allocated in shared memory and DDR3 . I used malloc to allocate an array. but the allocation failed. still the code runs till the end. Here is my code: #include <stdio.h> #include...
    on Mar 12, 2012

  • Forum Post: Implementation of intrinsic functions in C

    Donald Fleck67749
    Does TI provide an implementation of the intrinsic functions (_abs, _add2, etc) in C for the C66x? This enables debugging of DSP code in VisualC. I have a file from TI called C6xSimulator.c which I have used for the C64x. Is there a new version for the C66x? Thanks, Don
    on Mar 12, 2012

  • Forum Post: Moving text section in MSMC or DDR3

    Pankaj Kumar
    Hi, We are using Keystone family of Multicore DSP. We wanted to use most of L2 SRAM as data memory because cache coherancy is handled in hardware and one does not need to maintain it using software.Therefore, I am thinking to move text section in MSMC or DDR3. I am able to see some performance loss...
    on Mar 13, 2012

  • Forum Post: Re: How do the data pass through the internal ports and buses in C6670?

    Karthik Ramana Sankar
    Hi Daisuke, Yes you understanding is correct. All the data paths mentioned above are correct. No. The MSMC CorePac Slave Port is used only by the CorePAC MDMA transactions (which include load /store instructions).
    on Mar 13, 2012

  • Forum Post: How to configure MSMC SRAM?

    Mohamed Sohal
    Hi! How Multicore shared RAM in 6678 can be configured an L2 and L3 Cache. Is it possible to change the configuration in the code. Does SHARED RAM have any default configuration ? regards, Sohal
    on Mar 14, 2012

  • Forum Post: Re: EDMA3 Interrupt

    Karthik Ramana Sankar
    Hi Bharti, The following procedure should be followed for any ISR which handles interrupts routed through the CPINTCs: /* For interrupts routed through the chip-level INTC */ void CPINTC_ISR (Uint32 eventId) { /* Disable CPINTC0 Host interrupt (CPINTC output) */ CSL_CPINTC_disableHostInterrupt(cphnd...
    on Mar 15, 2012

  • Forum Post: NWRITE and NWRITE_R transactions taking more time then NREAD ( Throughput Measurement - DIRECTIO )

    Chaitanaya Chhibbar
    Hi, I have measured the throughput for different SRIO - direct IO transaction formats for TI DSP - 6618 using the bridge board setup. Problem Statement: Nread gives better throughput then Nwite and NwriteR. Measurement Setup: DSP on EVM 1 connected to DSP on EVM 2 using bridge board. ...
    on Mar 23, 2012

  • Forum Post: Re: PKTDMA and Descriptors/LInked RAM

    Karthik Ramana Sankar
    Hi Aamir, There is not much loss in performance when external linking RAM is used. However, I do not have figures supporting this. The external linking RAM is accessed by the QM_second master, whenever there is only pushing and popping of descriptors associated with the external linking RAM memory...
    on Apr 13, 2012
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