C6000 Multicore DSP

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C6000 Multicore DSP

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  • Forum Post: Hex6x NOR Flash Boot 6678

    Daniel S
    Hello. I am new to using the hex6x generation tool and boot code in general. Can anyone help me with the param settings? I want to boot the C6678 from EMIF NOR Flash (0x7000_0000). The flash is in 16 bit mode. The code is compiled/linked to run in L2SRAM (0x0080_0000) and runs well when loaded with emulator...
    on Sep 8, 2012

  • Forum Post: Re: Booting from NAND on evm6678l

    r_robotics
    We have two EVMC6678 boards. One seems to be a bit flaky. Repeating the steps on the other board provided much more sane results. However, after board reboot, no program seems to load. Again, the basic steps I'm doing are: Compile and test program create a *.dat file from *.out Write...
    on May 16, 2011

  • Forum Post: Re: Booting from NAND - round 2

    tscheck
    A couple things to check, it's hard to tell from the quick summary of steps above... First, the *.dat format is not the actual format to load into NAND, but if you followed the steps in: C:\Program Files\Texas Instruments\mcsdk_2_00_00_beta2\tools\writer\nand\docs\README.txt it should program...
    on Jun 2, 2011

  • Forum Post: Re: SRIO Issues on EVM6678

    Jean-luc
    Justin, I'm a newbie here, sorry if I'm not in the right thread. I'm very interested to sRIO and PCIe general setup. Please could you give me the TI link to download the pdk_C6678_1_0_0_9_beta2 package, I found the looback SRIO over socket example interesting, but I would like to...
    on Jun 8, 2011

  • Forum Post: Secondary Boot with PLL fix

    Jim Rondero
    Hello, In order to perform Ethernet boot, I wish to program the i2c eeprom on my EVM with the secondary boot example instead of the IBL. When running the secondary boot in debug mode it works a sends the BOOTP package as expected. But when I use the make file supplied and program it to the eeprom...
    on Jul 5, 2011

  • Forum Post: Booting a Sys/Bios application

    Jim Rondero
    Hello, I trying to boot a Sys/BIOS application from the NOR flash on the C6678 EVM, but with no success. I already booted the nor boot example and the post example. Now I compiled the BIOS Hello world template an made it write to the UART, but no matter what I try to do it doesn't work....
    on Jul 26, 2011

  • Forum Post: Nandboot for multicore sample application

    NARESH PATEL
    Hi, I have small sample application. I write it to Nand by using nand writer . Then after i perform nand boot . Application runs only for core 0.I want to run it on all six cores. Is it possible and how it is ? Thanks
    on May 4, 2011

  • Forum Post: Re: Nandboot for multicore sample application

    Ricardo Leber
    Dear Sandeep, I thank you for all the help you gave me. The development in which I am working is far more complicated than the example project of the LEDs. So it took me longer work, due to the location of the vectors and variables that should be in a shared area and others in local memory. The program...
    on Aug 8, 2011

  • Forum Post: Re: C6678 SRIO Boot

    Raj Sivarajan
    Brian, Also, there is a SRIO boot example in BIOS-MCSDK. Once you install the SDK, the default location is: C:\Program Files\Texas Instruments\mcsdk_2_00_0x_xx\tools\boot_loader\examples\srio This is a multicore example that uses DDR. At the end, you will see an output indicating a "Hello...
    on Sep 22, 2011

  • Forum Post: [TCI6618/6616] Boot parameter table of two-level bootloader using I2c and Ethernet

    Eric Liang
    Hi all, I am working on TCI6618's bootloader using I2c and Ethernet. But I can NOT make out the correct boot parameter table of Ethernet boot. By reading the user guide of bootloader (2011 version), there are several parameters not found in the GbE user guide, such as SGMII Rx / Tx / Aux Cfg register...
    on Nov 4, 2011

  • Forum Post: TMSC6678 bootloader info

    shrish mv
    hi, i am working on shannon evm c6678 ..SDK used are MCSDK 2_00_00_11 and pdk_c6678_1_0_0_11. I am studying the bootloader source present on mcsdk >tools>bootloader>ibl>src . Is there any document on how the bootloader is built ? ie how the different components are called and ...
    on Dec 5, 2011

  • Forum Post: Re: NOR Boot Problem in EVMC6678L (Rev1.0)

    tscheck
    A couple of comments: - First, update your MCSDK to the latest version: http://software-dl.ti.com/sdoemb/sdoemb_public_sw/bios_mcsdk/latest/index_FDS.html Your version is very old. The NOR writer procedure is different and may contain bug fixes from the version you are using. - It sounds like you...
    on Dec 15, 2011

  • Forum Post: Re: PCIe BAR Window Sizes for PCIe Boot

    Jonathan White
    Can someone at TI please answer the above question of 10th November. As I mentioned, the documents are unclear and inconsistent. In addition, I have been experimenting on an EVM board without the IBL installed (because the IBL would override the BAR Config DIP switches). The results (without IBL...
    on Dec 28, 2011

  • Forum Post: bootloader PLL workaround doubt

    shrish mv
    Hi all, I am using Shannon EVM c6678 , MCSDK 2_00_00_11 , and pdk_C6678_1_0_0_11. I have the following doubt with respect to the bootloader. In the TMS320C6678 silicon Errata it is mentioned that for boot modes other than i2c and spi, the bootloader should perform PLL workaround for stable...
    on Dec 29, 2011

  • Forum Post: Re: PCIe BAR Window Sizes for PCIe Boot

    Jonathan White
    Hi Arun, I checked the BAR window size as follows: Using a “fresh out of the box” EVM, set to PCIe Boot mode, I reset the EVM and use CCS to read the BAR registers, observing “all-zeros”, except that the prefetch bit is set for BAR 0. I then write 0xFFFFFFFF to each BAR...
    on Jan 11, 2012

  • Forum Post: Re: PCIe BAR Window Sizes for PCIe Boot

    Jonathan White
    Hi Arun, we know about the PLL Lock issue and the FPGA workaround. We have some EVMs that were re-flashed by us as mentioned in the PCIe doc, and some that are “fresh from factory” (i.e. not re-flashed). All of our EVMs boot properly. We see the 0x20BXXXXX address at the end of boot (non...
    on Jan 11, 2012

  • Forum Post: Core 1 L2SRAM usage by ROM boot-loader in PCIe boot

    Jonathan White
    If I load code to Core1 L2SRAM in the range local 0x0087FF9C (global 0x1187FF9C) to 0x0087FFFB, then the CorePAC never reaches _ c _int00. I can use the rest of the L2SRAM from 0x00800000 to 0x0087FF9B. Obviously 0x0087FFFC is reserved for the BootMagicAddress, but I see nothing in SPRUGY5A about...
    on Jan 17, 2012

  • Forum Post: Re: PCIe BAR Window Sizes for PCIe Boot

    Jonathan White
    Hi Arun, I just repeated the experiment. It now seems to work OK. The previous time I tried it (on 28th December 2011), I was connecting to the EVM too soon after powering up the EVM. To get the proper results, it is necessary to give the EVM time to reach Boot ROM Program Counter PC = @ 0x20B01270...
    on Jan 19, 2012

  • Forum Post: PCIe BAR Window Sizes for PCIe Boot

    Jonathan White
    The C66x DSP Bootloader User Guide (SPRUGY5A) Table 3-12 and Table 3-15 discuss how Windows 1 through 5 depend on the 4 BAR Config bits (e.g. as set by DIP switches on the EVM board), but the information is unclear to me. For example, Table 3-12 says “Window 1 size. The size is 32 MB * 2n...
    on Nov 10, 2011

  • Forum Post: Re: BOOT of a SYSBIOS project

    Jonathan White
    On Core 0 there is a secondary boot loader at L2SRAM location 0x00800000 to 0x0081FFFF. It is to work around the PLL Lock problem. The source code is in .../mcsdk_2_00_01_12/tools/boot_loader/ibl/src See file .../mcsdk_2_00_01_12/tools/boot_loader/ibl/src/make/ibl_c66x/ibl_init_image.rmd See...
    on Jan 25, 2012

  • Forum Post: Write two .out files to NAND and boot in different cores?

    Mohamed Sohal
    Hi all, I want to write the executable (.out) and have to boot it from NAND. But I have 2 .out files. One for CORE0 and one for the remaining 7 cores. How can I write these both and make them boot for the respective cores. EVMC6678LE CCSv5.0.23 Regards, Sohal
    on Jan 30, 2012

  • Forum Post: Re: question about 6670 bootloader

    Jonathan White
    There is some sample code that comes with the TI tools. If you installed at the default location, it would be here in your machine: C:\Program Files\Texas Instruments\mcsdk_2_00_01_12\tools\boot_loader
    on Feb 6, 2012

  • Forum Post: Re: TSM320c6670 Boot ROM

    Noryab
    I've reading the KeyStone Architecture SOC Security User Guide (<SPRUHC3>) , the C66x DSP Bootloader User Guide (<SPRUGY5>) , the KeyStone Architecture Bootloader User Guide (<SPRUGY5A>) and the TMS320C6670 Data Manual (<SPRS689C>) . They all briefly mention the two boot modes...
    on Feb 24, 2012

  • Forum Post: Re: Why is C6678 MPAX Segment 2 enabled at power-up

    Jonathan White
    Thanks Allen. The values I see certainly match the ones in xmc_setup (which I have pasted below). But the odd thing is I am not explicitly using a GEL file. Perhaps one gets loaded by default when connecting using CSS? Although that seems a bit intrusive. I will do more experiments in different...
    on Mar 8, 2012

  • Forum Post: Debugging the IBL - malloc failing, EVM failing to step through code

    Dan Christensen
    Hello, I'm trying to bring up a custom board with 2 C6678s. In an effort to change to a different booting strategy, I've been attempting to run the IBL interactively through CCS. This post ( http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/140644.aspx#513379 ) was very helpful....
    on Mar 6, 2012
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