C6000 Multicore DSP

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  • Forum Post: EDMA3 6678 Transfers failing for "larger" A and B counts

    Tim Wentz
    I'm going a matrix application, so part of it involves moving submatrices around in memory. I was initially excited about the EDMA 'tranpose'/'data sorting' technique, but when I included it, the transpose operation started returning incorrect results for larger than trivial-sized...
    on Jul 7, 2011

  • Forum Post: EDMA stopped generating completion interrupts

    Yishay Hayardeni
    Hi, I'm using a c6678 EVM. I am testing the EDMA LLD. I wrote a few test applications which worked fine up until a few days ago. When trying to solve another problem, I updated to the latest MCSDK 2.0 release. Since the update I don't get any interrupt for EDMA transfer completion. I also...
    on Aug 3, 2011

  • Forum Post: Initializing EDMA3 for TCP3D

    Bob Lin
    Hello, I’m using TCP3d over C6670 and having problem in initializing EDMA3 to transfer data (Config Regs) into TCP3 register. The code is given as below. Could someone help figuring out why EMDA3 does not work? Best Regards, Bob ======...
    on Sep 6, 2011

  • Forum Post: A strange problem about EDMA3

    Eric Mao
    Hi All, I use C6678 evm, I use the EDMA to move data from MSMC to DDR3. The DMA source address will change, but the destination address is fixed. Every time, move a cif image data. The first time, the data move to destinaton buffer correctly. but the others the data of destination buffer never change...
    on Oct 18, 2011

  • Forum Post: Problems/Questions for Interrupt triggered by EDMA completion on C6678

    Dongning Li
    I encountered some problems with EDMA completion interrupt, which was reported in my posting below: http://e2e.ti.com/support/embedded/f/355/p/137259/497771.aspx#497771 Instead of continuing that thread for my new findings, I create this new thread for my findings/problems/questions as below. In...
    on Oct 11, 2011

  • Forum Post: why is the time of call QDMA so long?

    Zhijun Wang
    The result of QDMA on my 6678 EVM board confuse me. why is the time of call QDMA_copy_fast is so long? Thank you! 6678,1GHz,EVM board My QDMA 1D-1D copy code: ---------------------------------------------------- void QDMA_copy_fast(Uint8 *src, Uint8 *dst, Uint32 len...
    on Nov 21, 2011

  • Forum Post: CRITICAL ERRORS while loading program to EVMC6678LE......!!!!

    Mohamed Sohal
    Hi all, We have created a project almost similar to the MCSDK image processing demo using CCS v5.0.23. with the edge detection function changed to some other image processing function. We created a new CCS RTSC empty project and copied the source files and so on making some necessary changes. We were...
    on Nov 25, 2011

  • Forum Post: Re: Transfer by Multicore Navigator vs EDMA3

    Derek Brown
    Miguel, The Multicore Navigator (QMSS and packet DMA) are typically used for packet based transfers, whereas the EDMA allows for more flexible data transfer configurations. Based on this distinction, some of peripherals are designed to use either the EDMA or the packet DMA for transferring data...
    on Dec 16, 2011

  • Forum Post: Re: Transfer by Multicore Navigator vs EDMA3

    Derek Brown
    Miguel, The Multicore Navigator is required for use with some peripherals. The queueing functionality provided by the Queue Manager works well for some peripherals so that several messages can be received and queued, and then processed in batches. Most of these peripherals also have the ability to...
    on Jan 10, 2012

  • Forum Post: core to core communication using EDMA3(6678)

    woonkyung kim
    Hello. I'm trying to copy a data from core0 l2 to core1 l2 using example in \pdk_C6678_1_0_0_11\packages\ti\csl\example\edma when i'm trying to copy from core0 l2 to core0 l2, it works well. but for core to core mem copy, i think it is not working well. i changed the code myParamSetup...
    on Feb 13, 2012

  • Forum Post: Re: Transfer by Multicore Navigator vs EDMA3

    Derek Brown
    Miguel, You should only have to use one transfer controller to fully utilize the bus. If you use multiple transfer controllers at the same time, then the bus will still be fully utilized, but it will be divided between the transfer controllers that are in use, causing your per channel performance...
    on Feb 15, 2012

  • Forum Post: DDR3 data transfer overhead!!!

    Mohamed Sohal
    Hi all, We have a data stored in the DDR3 memory. This data is accessed simultaneously by the 8 cores for processing. At this stage there is a possibility of memory read conflicts. How can we reduce this overhead and hence to optimize this memory read/write operations. Regards, Sohal
    on Jan 20, 2012

  • Forum Post: EDMA3 Intermediate chaining (for breaking up large transfers)

    Clement Mesnier
    Hi, My setup : C6678 EVM, CCS 5.1.1.00031, Compiler v3.3, mcsdk_2_00_05_17, pdk_C6678_1_0_0_17, edma3_lld_02_11_03_02 Background : I've been playing around EDMA3 for a few days now. I've successfully tested the edma_test.c examples that comes with the CSL. I've also tested...
    on Mar 14, 2012

  • Forum Post: Re: I need information of the memory throughput for the C6670L EVM.

    Derek Brown
    Daisuke, If you are using the transfer controllers attached to the CPU/3 teranet, then as you calculated, your maximum theoretical throughput will be 5333MB/s. Your throughput is reasonably close to that number. If you want to achieve better EDMA performance to DDR3, you can try using the EDMA...
    on Mar 15, 2012

  • Forum Post: Re: EDMA3 Interrupt

    Karthik Ramana Sankar
    Hi Bharti, The following procedure should be followed for any ISR which handles interrupts routed through the CPINTCs: /* For interrupts routed through the chip-level INTC */ void CPINTC_ISR (Uint32 eventId) { /* Disable CPINTC0 Host interrupt (CPINTC output) */ CSL_CPINTC_disableHostInterrupt(cphnd...
    on Mar 15, 2012

  • Forum Post: Re: I need information of the memory throughput for the C6670L EVM.

    Karthik Ramana Sankar
    Hi Daisuke, [Karthik]: According to my understanding, for EDMA throughput tests between CorePAC L2 and MSMC/DDR3, there should not be much difference in the throughput measurements, when using TCs connected to the CPU/2 TeraNet or the CPU/3 TeraNet. The throughput is limited by the fact that CorePAC...
    on Mar 19, 2012

  • Forum Post: Edma + INTC + CPINTC : Proper ISR

    Clement Mesnier
    Hi everyone, I have successfully implemented a simple block transfer using EDMA with an interruption. However I think that my ISR isn't complete. Can anyone help me figure out what is missing ? Here's a stripped down version of the code. By the way what does GEM mean ? Global...
    on Mar 21, 2012

  • Forum Post: C6678 EDMA3 example on C6670

    Ming-Che Lin
    Hello, I found out a EDMA3 example code edma_test.c from \ti\pdk_C6678_1_0_0_16\packages\ti\csl\example\edma. I used edma_test.c to run on C6670, but I got the results: [C66xx_0] ************************************************** [C66xx_0] ******************* EDMA Testing ***************** ...
    on Dec 13, 2011

  • Forum Post: RE: how to abort a EDMA3 transfer in progress?

    Karthik Ramana Sankar
    Lyndon, Adding to Chad's point. If an EDMA Transfer request is taking more time than expected for completing the transfer, then there can be two reasons for this to happen: 1) EDMA TR encounters an error condition and the DSP CPU should handle this EDMA TC error condition. Please, refer to...
    on May 9, 2012

  • Forum Post: RE: IPC Transport Mechanisms

    Karthik Ramana Sankar
    Hi Reddy, Please, find my answers inserted below: 3. I understand from one of the Ti's post is that even EDMA can do both jobs [point 1 and point 2] and it is much faster. Is it possible to MessageQ over EDMA3. [Karthik]: EDMA3 cannot be used for chip to chip communication. As far as I know...
    on May 9, 2012

  • Forum Post: RE: IPC Transport Mechanisms

    Karthik Ramana Sankar
    Hi Reddy, I would like to state my point more clearly here: Standalone EDMA3 cannot be used for chip to chip communication. Where as, EDMA coupled with Hyperlink can be used for chip to chip communications. As far as my knowledge, we do not have SYS/BIOS IPC layer implemented over EDMA3. The EDMA3...
    on May 15, 2012

  • Forum Post: RE: Which EDMA3 channel can be used to write data from DSP to TCP3D?

    Donald Fleck67749
    In the TMS320TCI6487 manual, Section 8.5.1 it says "The association of each synchronization event and DMA channel is fixed and cannot be reprogrammed". That is what I meant by a dedicated channel, i.e. channel 31 is dedicated to the TCP Transmit Event. In the TMS320C6670 Data Manual, in Tables...
    on Jun 12, 2012

  • Forum Post: Which EDMA3 channel can be used to write data from DSP to TCP3D?

    Donald Fleck67749
    In the TMS320TCI6487, EDMA3 channel 31 was used to write data from the DSP to the TCP2. In the C6670 there is no dedicated EDMA3 channel, so which EDMA3 channel can be used to write data from DSP to TCP3D? Can I use any CICn_OUTnn channel?
    on Jun 11, 2012

  • Forum Post: Mistake in KeyStone Architecture Viterbi Coprocessor (VCP2) User Guide SPRUGV6A—June 2011

    Donald Fleck67749
    I think Section 4.2.1 VCP2 Dedicated EDMA3 Resources is incorrect. This seems to be a cut-n-paste from Section 9.1.1 of TMS320TCI648x/9x DSP Viterbi-Decoder Coprocessor 2 (VCP2) User's Guide SPRUE09E May 2006–Revised December 2009. Section 4.2.1 implies there is only 1 instance of EDMA3 and...
    on May 16, 2012

  • Forum Post: RE: Mistake in KeyStone Architecture Viterbi Coprocessor (VCP2) User Guide SPRUGV6A—June 2011

    Donald Fleck67749
    I think there is a mistake in Section 4.2.2. In this section there is a reference to "TMS320C6472/TMS320TCI648x DSP Enhanced DMA (EDMA3) Controller User's Guide (SPRU727)". I think this reference should be changed to "Enhanced Direct Memory Access (EDMA3) Controller User Guide (SPRUGS5A...
    on Jul 11, 2012
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