C6000 Multicore DSP

Browse by Tags

C6000 Multicore DSP

Welcome to the C6000 Multicore DSP Section of the TI E2E Support Community. Ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers. To post a question, click on the forum tab then "New Post".

Sign In to Post
Tags
You have subscribed to this tag. To view or manage your tag subscriptions, click here.   Close
You have unsubscribed from this tag. To view or manage your tag subscriptions, click here.   Close
You are currently viewing:
320C6678 DDR3
Related Posts

  • Forum Post: C6678 DDR3 On-die Termination values

    Greg Reuter
    Hello Forum, Keystone DDR Memory Controller User Guide SPRUGV8C.pdf Section 4.23 describes DDR_PHY_CTRL_1. It contains bit fields IDLE_LOCAL_ODT, WR_LOCAL_ODT, and RD_LOCAL_ODT. These bit fields establish controller terminations. What are the termination values for the various bit-field values? We...
    on Aug 1, 2012

  • Forum Post: tms320c6678

    Avinash Neethi1
    Hello, I have certain questions on PLL. How to initialize the PLL in gel file and in U-boot setup. can you also explain the below parameters ibl.pllConfig[ibl_DDR_PLL].doEnable = 0; ibl.pllConfig[ibl_DDR_PLL].prediv = 1; ibl.pllConfig[ibl_DDR_PLL].mult = 12; ibl.pllConfig[ibl_DDR_PLL].postdiv = 2;
    on Aug 2, 2012

  • Forum Post: RE: tms320c6678

    Avinash Neethi1
    Chad, I have gone through both the PLL User Manual and TMS320C6678. But I can't find any thing how to calculate the multiplier, divider values of PLL. we are using system clock of 100Mhz and DDRCLK of 66.66Mhz. With reference from the TMS320C6678 data sheet pg.no 34 (2.5.3 PLL Boot Configuration...
    on Aug 3, 2012

  • Forum Post: TMS320C6678

    Avinash Neethi1
    Hello, I have gone through both the PLL User Manual and TMS320C6678. But I can't find any thing how to calculate the multiplier, divider values of PLL. we are using system clock of 100Mhz and DDRCLK of 66.66Mhz. With reference from the TMS320C6678 data sheet pg.no 34 (2.5.3 PLL Boot Configuration...
    on Aug 3, 2012

  • Forum Post: RE: tms320c6678

    Avinash Neethi1
    Hi, I got a clear idea now. what are the register that should be configured for proper operation. I have listed the registers can you let me know what registers should be configured and why? I have a in source file in that certain register are configured and certain registers are assumed as 0. Can...
    on Aug 6, 2012

  • Forum Post: RE: tms320c6678

    Avinash Neethi1
    Hi Chad, I got a clear idea now. what are the register that should be configured for proper operation. I have listed the registers can you let me know what registers should be configured and why? I have a in source file in that certain register are configured and certain registers are assumed as 0. Can...
    on Aug 6, 2012

  • Forum Post: Running code in emulation boot mode

    will Resnick
    Hi, So when I try to run my application in emulation boot mode, I get a load program error in the DDR memory. It works fine when I run the evmc6678l.gel file. I believe it fails because I have multiple sections being allocated in the DDR3 in my .cfg file. I am porting the evmv6678l.gel file into an...
    on Aug 17, 2012

  • Forum Post: RE: Running code in emulation boot mode

    will Resnick
    Randy, I was trying to understand how the functions called before module initialization worked. I didn't know if this was the correct place to call the init routine for the DDR ram. I will need to load the executable code from I2C in the near future and I know I can't use a gel file for that...
    on Aug 20, 2012

  • Forum Post: C6678 Ibis model updates?

    Massimo
    Hi, is the IBIS model on the C6678 product page (sprm537.zip dated Aug 2011) the most updated version? Thanks, Massimo
    on Aug 29, 2012

  • Forum Post: Initialise DDR in PCIe boot of v2 silicon

    Adrian Cox
    I'm updating a working c6678 PCIe endpoint system to v2 silicon. My goal is to drop the IBL and switch to the internal boot rom for PCIe booting. I'm testing this using an EVM with v2 silicon. Is it possible to carry out this sequence, or is something missing here: Fill in the DDR table...
    on Aug 29, 2012

  • Forum Post: RE: tms320c6678

    Avinash Neethi1
    (Please visit the site to view this file) Hi Chad, I want to know how to calculate the DQS routed length and clock routed length from the PCB length. there are two values in that is DQS and DQS# , In the clock we have two values for P and N value. How to calculate the values from this excel sheet.I...
    on Aug 30, 2012

  • Forum Post: RE: DDR3 PHY Calculation

    Avinash Neethi1
    Hi Tom, The PHY_CALC spreadsheet requires the value from DQS(0-7), CK(0-7), DQS_ECC,CK_ECC. But In the Excel Sheet i attached consist of DQS(0-7), DQS#(0-7), DDR3_CLKOUTP& DDR3_CLKOUTN four set of clock routed length are there how to calculate the values as required for PHY_CALC spreadsheet . ...
    on Aug 31, 2012

  • Forum Post: DDR3 legnth of Clock , addr and command line compared with length of data and data strobe

    Gasparrini Piero
    Hello, In the document "DDR3 Design Requirements for KeyStone Devices" SPRABI1A- April 2011, I have found in the paragraph ( 4.3.1.10 Write Leveling Limit Impact on Routing ) the constraint regarding the skew between the clock, addr ,command line and data , data strobe. In the table 16 and...
    on Sep 3, 2012

  • Forum Post: RE: DDR3 PHY Calculation

    Avinash Neethi1
    Hi Tom , I have attached the Schematic page of the DDR3 with this mail. I have understand the DQS section now. Can you provide the calculation method for clock . (Please visit the site to view this file) Regards, Avinash
    on Sep 4, 2012

  • Forum Post: RE: DDR3 PHY Calculation

    Avinash Neethi1
    Hi Tom , we want to find the average of the DDR3_CLKOUTP0 & DDR3_CLKOUTN0 for U11 to U17, U11 to U18, U11 to U19, U11 to U20, U11 to U16 and substitute them in the CLK(0-7). Else we want to take any one of the parameter ( DDR3_CLKOUTP0 & DDR3_CLKOUTN0) and substitute them in CLK(0-7). Regards...
    on Sep 4, 2012

  • Forum Post: RE: DDR3 PHY Calculation

    Avinash Neethi1
    Hi Tom, I can't get the term correctly .The Differential Pair routing length means [(DDR3_CLKOUTP0 + DDR3_CLKOUTN0)/2] Am i correct. Regards, Avinash
    on Sep 4, 2012

  • Forum Post: Can't find a source file at "/sim/sds12/scratch/tsuch_rtsbuild_dflcmp2507.dal.design.ti.com_23248_linux/c60_rts/SHARED/feof.c"

    may may92122
    Can't find a source file at "/sim/sds12/scratch/tsuch_rtsbuild_dflcmp2507.dal.design.ti.com_23248_linux/c60_rts/SHARED/feof.c" Locate the file or edit the source lookup path to include its location. How to solve this problem?
    on Sep 9, 2012

  • Forum Post: Can I only use 64-bit data types with C6678 DDR3 ECC enabled?

    Greg Reuter
    Hi, In SPRUHH6.pdf, page 41 (2-27) section 2.16 there is a note that says: "...A write access with byte count that is not a multiple of 64-bit quanta, or with a non-64-bit-aligned address performed within the address range protected by ECC, will result in a write ECC error interrupt..."...
    on Sep 13, 2012

  • Forum Post: DMA transfer issue (Referring PDK sample - PING PONG Global region)

    Mohamed Sohal
    Dear All, I'm working with C6678 using CCS v5.1.1... I'm trying to do a basic copy using EDMA. I'm referring to edma sample given with PDK Package. (C:\Program Files\Texas Instruments\pdk_C6678_1_0_0_9_beta2\packages\ti\csl\example\). I have a text file (say 1.txt) which contains a...
    on Sep 21, 2012

  • Forum Post: Subframe DMA transfer issue!

    Mohamed Sohal
    Hi All, I'm working on C6678 and CCS v5.1.1. I have a buffer gRxBuffer on DDR3. I want to copy a small portion of this to a local buffer tempin. My present code is like the following: for(m = 511; m >= 256; m--) { tempin [m] = *( gRxBuffer + (p * offset1) + (i * row_width)+ m) ; // p and...
    on Oct 10, 2012

  • Forum Post: error in downloading image... to C6678 shannon.

    Anshul Maheshwari
    I am using the Tomahowk c6486, and have built the dimtesthd on linux host machine. Then i have run it. It gives the mxp prompt where i have submitted an script to laod an application. When the downlaoding compeleted it gives the message like... ............. ............. cc dnld 0 0 OK wait...
    on Oct 10, 2012

  • Forum Post: Keystone Core interface set up.

    Hector Rivera
    All, I have a customer that is asking if they can configure a keystone device that one of the cores has ownership of a specific interface for sample the PCIe. Below is the customer question as they sent it to me. Is there a way to have a particular CPU core who “owns” a given PCIe or...
    on Dec 3, 2012

  • Forum Post: RE: how to use IBL to boot from emif nor flash?

    asdf lea
    thanks Thomas. I know that IBL support elf format.and i mean i use IBL to boot the *.out file in emif nor flash.
    on Dec 24, 2012

  • Forum Post: Non initialization for MSMCSRAM variables using 7.2 compiler version

    C. García
    Hi, I defined for my application arrays in MSMCSRAM using #pragma DATA_SECTION ..... I want to avoid system initialization of those variables. I tried to use #pragma NOINIT(x), but I received warning that NOINIT is not recognized by the compiler. I saw in the compiler version that I'm using...
    on Dec 28, 2012

  • Forum Post: How to run any code by using all cores of C6678L .../?

    studinstru sggs
    Hi, I am using TMS320C6678 processor with 8 cores (core 0,...,core 7). I am trying to run the H264 HP Decoder on this evm with CCSv5.3 ....... The mentioned code is having config files where I can select the number of cores used to run the code on evm . I made core number :4 in .cfg file ,but...
    on Jan 24, 2013
12

All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with respect to these materials. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.

Content on this site may contain or be subject to specific guidelines or limitations on use. All postings and use of the content on this site are subject to the Terms of Use of the site; third parties using this content agree to abide by any limitations or guidelines and to comply with the Terms of Use of this site. TI, its suppliers and providers of content reserve the right to make corrections, deletions, modifications, enhancements, improvements and other changes to the content and materials, its products, programs and services at any time or to move or discontinue any content, products, programs, or services without notice.

TI Worldwide | Contact Us | my.TI Login | Site Map | Corporate Citizenship | mobile m.ti.com (Mobile Version)

TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs and
embedded processors, along with software, tools and the industry’s largest sales/support staff.

© Copyright 1995-2013 Texas Instruments Incorporated. All rights reserved.
Trademarks | Privacy Policy | Terms of Use