C6000 Multicore DSP

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320C6678
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  • Forum Post: C6678 srio interrupt

    qbliu
    hi,all: i want to generate the srio dio Tx Completion Isr in my route,but it can't. Please find out where is the fault : 1、i use CSL_SRIO_SetDoorbellRoute(hSrio, 1) to map the doorbell interrupt to INTDST16, LSU interrupt => INTDST0-15; 2、 CSL_SRIO_RouteLSUInterrupts (gtSrioDioOperaInfo...
    on Jul 23, 2012

  • Forum Post: RE: C6678 DDR3 Controller Initialization

    Avinash Neethi1
    Hi RandyP, Thanks for your confirmation i have got the gel file from the site. formation . which data sheets should be taken for the DDR3 memory controller configuration. Hardware Design Guide for KeyStone Devices or KeyStone DSP DDR3 Implementation Guidelines or DDR3 Design Requirements for KeyStone...
    on Jul 31, 2012

  • Forum Post: tms320c6678

    Avinash Neethi1
    Hello, I have certain questions on PLL. How to initialize the PLL in gel file and in U-boot setup. can you also explain the below parameters ibl.pllConfig[ibl_DDR_PLL].doEnable = 0; ibl.pllConfig[ibl_DDR_PLL].prediv = 1; ibl.pllConfig[ibl_DDR_PLL].mult = 12; ibl.pllConfig[ibl_DDR_PLL].postdiv = 2;
    on Aug 2, 2012

  • Forum Post: RE: tms320c6678

    Avinash Neethi1
    Chad, I have gone through both the PLL User Manual and TMS320C6678. But I can't find any thing how to calculate the multiplier, divider values of PLL. we are using system clock of 100Mhz and DDRCLK of 66.66Mhz. With reference from the TMS320C6678 data sheet pg.no 34 (2.5.3 PLL Boot Configuration...
    on Aug 3, 2012

  • Forum Post: TMS320C6678

    Avinash Neethi1
    Hello, I have gone through both the PLL User Manual and TMS320C6678. But I can't find any thing how to calculate the multiplier, divider values of PLL. we are using system clock of 100Mhz and DDRCLK of 66.66Mhz. With reference from the TMS320C6678 data sheet pg.no 34 (2.5.3 PLL Boot Configuration...
    on Aug 3, 2012

  • Forum Post: regarding nand boot in c6678

    GS Vinoth
    Hello, With the help of image processing demo, FDK algorithm was developed in c6678. the ccs version is 5.1.1.00031. Now i have two out files. One that is to be loaded to master.out --> core 0 and another, slave.out to all other cores. My task is to place the bin file into NAND and when power...
    on Aug 3, 2012

  • Forum Post: RE: tms320c6678

    Avinash Neethi1
    Hi, I got a clear idea now. what are the register that should be configured for proper operation. I have listed the registers can you let me know what registers should be configured and why? I have a in source file in that certain register are configured and certain registers are assumed as 0. Can...
    on Aug 6, 2012

  • Forum Post: RE: tms320c6678

    Avinash Neethi1
    Hi Chad, I got a clear idea now. what are the register that should be configured for proper operation. I have listed the registers can you let me know what registers should be configured and why? I have a in source file in that certain register are configured and certain registers are assumed as 0. Can...
    on Aug 6, 2012

  • Forum Post: RE: C6672 PCIe outbound read question

    Chi39519
    Steven I had initially set to "ENDIAN=2". So, I tried at "ENDIAN=0". But that did not work correctly (ENDIAN=0 and ENDIAN=2 is same　result.). The write operation is correctly, but the read operation is not correctly. What's the difference in the write and read operation...
    on Aug 7, 2012

  • Forum Post: Running code in emulation boot mode

    will Resnick
    Hi, So when I try to run my application in emulation boot mode, I get a load program error in the DDR memory. It works fine when I run the evmc6678l.gel file. I believe it fails because I have multiple sections being allocated in the DDR3 in my .cfg file. I am porting the evmv6678l.gel file into an...
    on Aug 17, 2012

  • Forum Post: RE: Running code in emulation boot mode

    will Resnick
    Randy, I was trying to understand how the functions called before module initialization worked. I didn't know if this was the correct place to call the init routine for the DDR ram. I will need to load the executable code from I2C in the near future and I know I can't use a gel file for that...
    on Aug 20, 2012

  • Forum Post: C6678 SGMII0 link is not up.

    Sean
    Hi We have a custom board with 4 C6678 DSPs connecting to a Marvell quad PHY 88E1240 through SGMII0 port. I run internal emac loopback test using your PA_emacExample_exampleProject (change port from SGMII1 to SGMII0), the test is passed without checking SGMII Link status. When I try to test with SGMII...
    on Aug 20, 2012

  • Forum Post: SPI CSL for c6678

    will Resnick
    Hi, Is there a SPI or UART Chip Support Library for the C6678? I only see one for the GPIO. Will
    on Aug 21, 2012

  • Forum Post: Unable to add Mac Address on c6678

    will Resnick
    The only time I can add the Mac Address and then register the EMAC is when I re-start the EVM and then load the evmc6678l.gel file. When I re-start the application in the debugger, I get the Add-MACAddress failed. Why is this? Will
    on Aug 21, 2012

  • Forum Post: RE: regarding nand boot in c6678

    GS Vinoth
    Got the hello world out from NAND boot. Thanks for the support provided by all. and TI support was excellent . Specail thanks to Jose Frangline for his continuous support. The mistakes we found out was, We were copying the i2cnandboot_evm6678l.out into the NAND writer and changed the name to app...
    on Aug 22, 2012

  • Forum Post: Initialise DDR in PCIe boot of v2 silicon

    Adrian Cox
    I'm updating a working c6678 PCIe endpoint system to v2 silicon. My goal is to drop the IBL and switch to the internal boot rom for PCIe booting. I'm testing this using an EVM with v2 silicon. Is it possible to carry out this sequence, or is something missing here: Fill in the DDR table...
    on Aug 29, 2012

  • Forum Post: RE: tms320c6678

    Avinash Neethi1
    (Please visit the site to view this file) Hi Chad, I want to know how to calculate the DQS routed length and clock routed length from the PCB length. there are two values in that is DQS and DQS# , In the clock we have two values for P and N value. How to calculate the values from this excel sheet.I...
    on Aug 30, 2012

  • Forum Post: regarding Multi core deployment

    GS Vinoth
    Hello All, EVM used is c6678le. I am presently using MAD to deploy two .out files, master.out in core 0 and slave.out in all other cores.The idea is to boot from NAND . Since i am new to this i was trying to work out the demo walk through provided in the MAD user guide. I was trying the prelinker mode...
    on Aug 31, 2012

  • Forum Post: RE: DDR3 PHY Calculation

    Avinash Neethi1
    Hi Tom, The PHY_CALC spreadsheet requires the value from DQS(0-7), CK(0-7), DQS_ECC,CK_ECC. But In the Excel Sheet i attached consist of DQS(0-7), DQS#(0-7), DDR3_CLKOUTP& DDR3_CLKOUTN four set of clock routed length are there how to calculate the values as required for PHY_CALC spreadsheet . ...
    on Aug 31, 2012

  • Forum Post: RE: DDR3 PHY Calculation

    Avinash Neethi1
    Hi Tom , I have attached the Schematic page of the DDR3 with this mail. I have understand the DQS section now. Can you provide the calculation method for clock . (Please visit the site to view this file) Regards, Avinash
    on Sep 4, 2012

  • Forum Post: RE: regarding Multi core deployment

    GS Vinoth
    I have some doubts regarding the MAD utility. I was following the prelinker mode and using the MAD user guide… With the example demo walk through I was able to produce the c6678_le.bin. And i want the bin file to be loaded to NAND. I have certain doubts regarding NAND booting... the memory...
    on Sep 4, 2012

  • Forum Post: RE: DDR3 PHY Calculation

    Avinash Neethi1
    Hi Tom , we want to find the average of the DDR3_CLKOUTP0 & DDR3_CLKOUTN0 for U11 to U17, U11 to U18, U11 to U19, U11 to U20, U11 to U16 and substitute them in the CLK(0-7). Else we want to take any one of the parameter ( DDR3_CLKOUTP0 & DDR3_CLKOUTN0) and substitute them in CLK(0-7). Regards...
    on Sep 4, 2012

  • Forum Post: RE: DDR3 PHY Calculation

    Avinash Neethi1
    Hi Tom, I can't get the term correctly .The Differential Pair routing length means [(DDR3_CLKOUTP0 + DDR3_CLKOUTN0)/2] Am i correct. Regards, Avinash
    on Sep 4, 2012

  • Forum Post: Can't find a source file at "/sim/sds12/scratch/tsuch_rtsbuild_dflcmp2507.dal.design.ti.com_23248_linux/c60_rts/SHARED/feof.c"

    may may92122
    Can't find a source file at "/sim/sds12/scratch/tsuch_rtsbuild_dflcmp2507.dal.design.ti.com_23248_linux/c60_rts/SHARED/feof.c" Locate the file or edit the source lookup path to include its location. How to solve this problem?
    on Sep 9, 2012

  • Forum Post: sgmii can link but cannot connnect

    jie wang75279
    Hi all, we have designed a c6678 board based on the EVM6678, but we use a Broadcom BCM5461S phy instead Marvel and have it connected to SERDES port 0 instead of port 1 (which is connected to an FPGA but currently not used),The SRIO/SGMII clock input frequency is 156.25MHz istead of 312.5MHz on C6678...
    on Sep 20, 2012
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