C6000 Multicore DSP

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6670
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  • Forum Post: Use of Shared Code Program Memory

    FeruzM
    Hi, I wonder if someone can guide me in memory management on 6670. I want to try Use of a shared message buffer for large array allocated from DDR, section 6.3 of http://www.ti.com/lit/an/sprab27a/sprab27a.pdf mentioning use of formula <base address> + <per-core-area size> ×...
    on Sep 26, 2011

  • Forum Post: ISR

    RAHUL SHARMA91013
    Hi I have a very basic question . I am working on C6670. Can i invoke another interrupt in an ISR itself ? for example ISR() { some_queue_push_operation_foo( ) ; // this push invokes another ISR } This is some kind of recursive interrupt. With Regards Rahul Sharma
    on May 1, 2012

  • Forum Post: SRIO Idle2 support

    Erick Higa
    I was wondering if the 667x SRIO was capable of IDLE2 (SRIO Gen2). As far as I could tell from the Keystone SRIO doc, IDLE2 is only supported w/ speeds >5.5 Gbps, however it should be possible to set devices up. Any info on this would be greatly appreciated. Thanks, Erick
    on May 4, 2012

  • Forum Post: RE: SRIO Idle2 support

    Karthik Ramana Sankar
    Hi Erick, C667x SRIO does not support IDLE2 sequences. It supports only IDLE1 sequences and the max baud rate supported is 5 gbps. Section 1.2 "RapidIO Feature Support in SRIO" of SRIO users guide mentions "Support for IDLE1 and IDLE2", which is incorrect and will be updated in...
    on May 4, 2012

  • Forum Post: C6670 VCP2_A power domain

    Donald Fleck67749
    In the TMS320C6670 user manual (SPRS689D March 2012) in Table 7-6 there is no mention of VCP2_A. In which power domain is it?
    on May 14, 2012

  • Forum Post: Mistake in KeyStone Architecture Viterbi Coprocessor (VCP2) User Guide SPRUGV6A—June 2011

    Donald Fleck67749
    I think Section 4.2.1 VCP2 Dedicated EDMA3 Resources is incorrect. This seems to be a cut-n-paste from Section 9.1.1 of TMS320TCI648x/9x DSP Viterbi-Decoder Coprocessor 2 (VCP2) User's Guide SPRUE09E May 2006–Revised December 2009. Section 4.2.1 implies there is only 1 instance of EDMA3 and...
    on May 16, 2012

  • Forum Post: RE: problem in using MAD tools

    Amandeep Singh
    but when i use " /ccsv5/tools/compiler/c6000/include" path now i am gettin the following error: cl6x -c --abi=elfabi -g --mem_model:data=far -fr=obj -I "C:/Program Files/Texas Instruments/ccsv5/tools/compiler/c6000/include"/include -I../src ../src/printf.c --output_file obj/printf...
    on May 23, 2012

  • Forum Post: problem in booting thorugh IBL in TFTP mode

    Amandeep Singh
    hi i am using IBL in C6670 to boot it through the TFTP mode of i2c. when i use the example given in the IBL with set of steps given,it works fine. But when i follow the same steps to send my appliaction to DSP through TFTP it doesnot get stopped after getting all the packets. it again searches...
    on May 25, 2012

  • Forum Post: SRIO Doorbell Source

    Erick Higa
    Hi all, I was wondering if there was a way to get the source ID of a sender when receiving a doorbell. We need to be able to know/figure out what source ID is sending the SRIO doorbell so that we can take the appropriate action. We are looking at a network that could have more than 64 nodes, so we'll...
    on May 30, 2012

  • Forum Post: LTE release 3 software

    Pankaj Kumar
    Hi, The underlined text I have copied from a TI document, where they describe their platform for LTE usage. Here is a discussion about The LTE release 3 software for PHY functions. We are using TI C6670 DSP for LTE development, how can I get access to this software to accelerate our development...
    on May 30, 2012

  • Forum Post: Which EDMA3 channel can be used to write data from DSP to TCP3D?

    Donald Fleck67749
    In the TMS320TCI6487, EDMA3 channel 31 was used to write data from the DSP to the TCP2. In the C6670 there is no dedicated EDMA3 channel, so which EDMA3 channel can be used to write data from DSP to TCP3D? Can I use any CICn_OUTnn channel?
    on Jun 11, 2012

  • Forum Post: RE: Which EDMA3 channel can be used to write data from DSP to TCP3D?

    Donald Fleck67749
    In the TMS320TCI6487 manual, Section 8.5.1 it says "The association of each synchronization event and DMA channel is fixed and cannot be reprogrammed". That is what I meant by a dedicated channel, i.e. channel 31 is dedicated to the TCP Transmit Event. In the TMS320C6670 Data Manual, in Tables...
    on Jun 12, 2012

  • Forum Post: RE: BCP Simulation on CCS

    david wang1
    Any IT Forum Fellow answer this question: C6670 has the same function as TCI6618 (from data manual yes they are same), or C6670 has some restriction? thanks
    on Jun 14, 2012

  • Forum Post: TCP3D, 3GPP and number of MAP decoders

    Donald Fleck67749
    In the TCP3D User Guide, in several places it says the number of MAP decoders is 1 for 3GPP (p. 41, 53, 103). But on p.43 it implies there are 2 MAP decoders for 3GPP because you calculate 2 sets of initial beta states, one for the first MAP decoder and one for the second MAP decoder.
    on Jun 14, 2012

  • Forum Post: TCP3D User Guide, mistake regarding beta states

    Donald Fleck67749
    In Section 3.1 it says "Calculation of initial beta states from tail bits (3GPP only)". But in Section 3.3.8 it implies the initial beta states are required for 3GPP and LTE.
    on Jun 14, 2012

  • Forum Post: RE: TCP3D, 3GPP and number of MAP decoders

    Donald Fleck67749
    Hello Arun, I plan to use it in single-buffer mode. In that case, would the number of MAP decoders be 1 or 2? Thanks, Don
    on Jun 19, 2012

  • Forum Post: Mistake in pdk_C6670_1_0_0_17\packages\ti\csl\cslr_tcp3d_dma.h

    Donald Fleck67749
    Regarding these definitions: #define CSL_TCP3D_DMA_TCP3D_IC_CFG2_P0_CRC_ITER_PASS_MATCH1 (0x00000000u) #define CSL_TCP3D_DMA_TCP3D_IC_CFG2_P0_CRC_ITER_PASS_MATCH2 (0x00000001u) #define CSL_TCP3D_DMA_TCP3D_IC_CFG2_P0_CRC_ITER_PASS_MATCH3 (0x00000000u) #define CSL_TCP3D_DMA_TCP3D_IC_CFG2_P0_CRC_ITER_PASS_MATCH4...
    on Jun 21, 2012

  • Forum Post: SRIO booting example not working

    Amandeep Singh
    Hi all I am using C6670 EVM in SRIO boot mode and m trying to boot one DSP from other using SRIO interface. i have tried the example given in the MCSDK but i am not able to boot the DSP. the problem is m not getting the prints of booting on the tera term as given in the example. please suggest...
    on Jun 25, 2012

  • Forum Post: RE: SRIO booting example not working

    Amandeep Singh
    hi the link between the 2 DSPs is established and I am getting the prints in CCS console about the DDR init and BOOT CODE transfer through SRIO successful. but how can i check that it has been transferered succesfully as m not getting the prints from booting DSP on tera term. please suggest. ...
    on Jun 25, 2012

  • Forum Post: RE: SRIO booting example not working

    Amandeep Singh
    yes i am using two c6670 boards (TMDXEVM6670L). thanks and regards Amandeep singh
    on Jun 26, 2012

  • Forum Post: RE: SRIO booting example not working

    Amandeep Singh
    Hi Yes I am getting the port ok on the connected port. I am using the DIO mode The whole procedure which I am carrying out is as follows: I have made the dip switch setting of both the modes to boot from SRIO boot mode. Then connected the booting EVM to the PC’s serial port using...
    on Jun 28, 2012

  • Forum Post: Verify failed when recoverying the factory image on TMDSEVM6670LE

    nf bj
    I just followed the steps in program_evm_userguide.pdf,using DSS script to recovery all the images in eeprom,nor and nand. First,I met a question that:An invalid processor ID has been found.and unabe to start the debug server.And I got the key:just use CCS5.1 to generate a new ccxml to replace the...
    on Jul 3, 2012

  • Forum Post: RE: HWI

    Karthik Ramana Sankar
    Hi Rahul, In the first place why do you want to achieve priority inversion (A lower priority task indirectly preempting a higher priority task)? Your approach of moving functions like disable,clear and enable of interrupts (sys/bios Cpintc) to a different task/SWI from the HWI, will result in missing...
    on Jul 11, 2012

  • Forum Post: RE: HWI

    RAHUL SHARMA91013
    Hi Karthik Thanks for the reply ! I started initially with the approach you are telling ( which is ideal one) and it worked perfectly. I have some timing constraints in the processing and i am receiving messages for the advanced Sub frames ( LTE ). At times , it is more important to do present...
    on Jul 12, 2012

  • Forum Post: Issues on PRACH with C6670

    Lee Chong
    Hi All, I have noticed few issues while running the example PRACH code given by TI. As per the release notes document "Release Notes for 02.00.00 UMTS_LTE.pdf", in page 7, it says that, "A new function, LTELIB_cplxMac is now included to facilitate using the FFTC to extract the same...
    on Sep 17, 2012
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