Hi, I've seen several cases of our custom DM365 based DVR design freeze up, and when JTAG connecting to diagnose the issue, the state of PC and registers seems to point at an ARM exception, however in the wrong vector address space. The ARM TRM mentions the VINITHI signal could set the vector address to 0xffff0000, but the TMS320DM36x ARM Subsystem guide mentions that it should be always in the 0x00000000 low range. I see that UBL startup code sets up CP15 correctly to the low vector address space. Our applications are not intentionally changing anything in the supervisor processor CP15 registers, is it possible that this is some spurious error on the DM365 CPU core? I don't seem mention of this in the errata.
CPU Registers PC 0xFFFF0010 Core Register SP 0xC0433A2C Core Register LR 0xFFFF0330 Core Register CPSR 0x20000097 Core Register R0 0xC0433A2C Core Register R1 0xFBAD0000 Core Register R2 0x4096A000 Core Register R3 0x00000000 Core Register R4 0x00000000 Core Register R5 0x00283B34 Core Register R6 0x00283A88 Core Register R7 0x00000001 Core Register R8 0x409546C4 Core Register R9 0x00000000 Core Register R10 0x4096A000 Core Register R11 0xBEFE3934 Core Register R12 0x00283B28 Core Register
ffff0010: FFFFFFFF .word 0xFFFFFFFF ffff0014: EA00009A B 0xFFFF0284 ffff0018: EA0000FA B 0xFFFF0408 ffff001c: EA000078 B 0xFFFF0204 ffff0020: EA0000F7 B 0xFFFF0404 ffff0024: 00000000 ANDEQ R0, R0, R0
And another case
PC 0xFFFF000C Core Register SP 0xC0433A2C Core Register LR 0xFE7B0058 Core Register CPSR 0xA0000097 Core Register N 1 Z 0 C 1 V 0 Q 0 A 0 I 1 F 0 T 0 Mode 10111 R0 0x00000000 Core Register R1 0x00000001 Core Register R2 0x002F17A8 Core Register R3 0x00000000 Core Register R4 0x00000000 Core Register R5 0x4096A000 Core Register R6 0x002F17A8 Core Register R7 0x002F1708 Core Register R8 0x40022ED0 Core Register R9 0x00000FF0 Core Register R10 0x00000001 Core Register R11 0x40023370 Core Register R12 0x409546C4 Core Register
And another case:
PC 0xFFFF000C Core Register SP 0xC0433A2C Core Register LR 0xFE7B0058 Core Register CPSR 0x00000097 Core Register N 0 Z 0 C 0 V 0 Q 0 A 0 I 1 F 0 T 0 Mode 10111 R0 0x00000000 Core Register R1 0x0025E8D8 Core Register R2 0xE18F600C Core Register R3 0x00000000 Core Register R4 0xBEDF93F0 Core Register R5 0x8F57D7FF Core Register R6 0x401625A4 Core Register R7 0x33713001 Core Register R8 0xE1A03F00 Core Register R9 0x00000000 Core Register R10 0x40025000 Core Register R11 0xBEDF936C Core Register R12 0x00000000 Core Register
ffff000c: EA9F0010 B 0xFE7B0054 ffff0010: EA0000BB B 0xFFFF0304 ffff0014: EA00009A B 0xFFFF0284 ffff0018: EA0000FA B 0xFFFF0408 ffff001c: EA000078 B 0xFFFF0204
CP15 register is set by the kernel while booting up just before enabling the MMU to point the vector table to 0xffff0000. Hope this clarifies your doubt.
Also JTAG will freeze when you're connecting while kernel is running. This behavior is because MMU is enabled and the addresses are virtual.
-Renjith | www.pathpartnertech.com | Verify the answer if you think your query is resolved
Thanks! I'll look over this part of the kernel arch code.
Do you mind telling us what your problem turned out to be? We've got a failure with the same symptoms and I'm looking for clues.
Root cause unknown, suspect DDR controller or DDR parts.
Downclocking the entire ARM subsystem via UBL seemed to improve stability...
Can you describe your problem? What is the exact use case and behavior, along with complete logs.
Thanks Mitch and Renjith. Our problem turned out to be DDR drive strength. Jeff's reply in this post http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/100/t/64431.aspx put me on to the issue.
Since we reduced the drive strength our board has been stable.
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with respect to these materials. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.