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TI Home » TI E2E Community » Support Forums » Digital Signal Processors (DSP) » DaVinci™ Video Processors » DM3x DaVinci Video Processor Forum » booting failure case on checking MDSTAT flag.
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booting failure case on checking MDSTAT flag.

booting failure case on checking MDSTAT flag.

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SEUNGSIK KWAK
Posted by SEUNGSIK KWAK
on May 02 2012 14:20 PM
Intellectual590 points

Hi All,

I have an interesting boot failure on UBL code. What I have been working on is custom DM365 and it is a kind of video recorder after H264 compression, simply speaking. For stress test, we make a test schedule which lets DM365 recode H264 video data for given time, e.g 3 minutes and have POR reset. The reset is done by external MSP430. It works fine first couple of hours, then booting fails on DEVICE_LPSCTransition function of UBL code. It has been observed by JTAG and CCS.  

The exact location where the UBL is spinning is below.

void DEVICE_LPSCTransition(Uint8 module, Uint8 domain, Uint8 state)
{
// Wait for any outstanding transition to complete
while ( (PSC->PTSTAT) & (0x00000001 << domain) );

// If we are already in that state, just return
if (((PSC->MDSTAT[module]) & 0x1F) == state) return;

// Perform transition
PSC->MDCTL[module] = ((PSC->MDCTL[module]) & (0xFFFFFFE0)) | (state);
PSC->PTCMD |= (0x00000001 << domain);

// Wait for transition to complete
while ( (PSC->PTSTAT) & (0x00000001 << domain) );

// Wait and verify the state
while (((PSC->MDSTAT[module]) & 0x1F) != state);
}

where module is LPSC_DDR2(13) and state is PSC_ENABLE(3). The register value (PSC->MDSTAT[module]) & 0x1F) is not equal. Also, If the PC count is changed to next instuction, usually booting is successful as long as MDSTAT is "ready to go" like 0xXXXX01FXX.  Normally a couple of Watchdog reset fixes the issue.

Any suggestion and advice will be helpful.

Regards,

SK

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  • Renjith Thomas
    Posted by Renjith Thomas
    on Jun 13 2012 10:17 AM
    Guru26150 points

    SK,

    Can you put a timeout in this loop and see whether the error occurs or not? Also make sure that the timeout is good enough so that other devices also doesn't fail. 

    Also you can try doing a sync-reset of the DDR module just before this loop?

    -Renjith | www.pathpartnertech.com | Verify the answer if you think your query is resolved

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  • SEUNGSIK KWAK
    Posted by SEUNGSIK KWAK
    on Jun 13 2012 14:51 PM
    Intellectual590 points

    Hi Renjith,

    Thank you for the reply. Yes. I have done that - adding some timeout and sync-reset as I remembered. On the testing it does help a little bit but system hang still occurs.  I guess that there would be some timing issue. The issue disappeared once I put watchdog reset after some timeout.

    Regards,

    SK

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