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H/W 4-bit ECC correction code in Linux kernel 2.6.18 for DM365

Ivy Liu
Intellectual 730 points

Hi ,

I was testing H/W 4-bit ECC correction in DM365 and I found the correction code in kernel 2.6.18 is different from the one in 2.6.32 and the UBL code in post  http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/100/p/182730/708236.aspx#708236.

In function nand_davinci_4bit_compare_ecc() in Linux kernel 2.6.18, the code for checking NAND_FSR is

 /*
  * Wait for the corr_state field (bits 8 to 11)in the
  * NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3.
  */

 do {
  iserror = __raw_readl(info->emifregs + NANDFSR);
  iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
  iserror = iserror >> 8;
 } while ((0x0 != iserror) &&
   (0x1 != iserror) &&
   (0x2 != iserror) &&
   (0x3 != iserror));

 

But the correction code in Kernel 2.6.32 and UBL is,

 /*
  * ECC_STATE field reads 0x3 (Error correction complete) immediately
  * after setting the 4BITECC_ADD_CALC_START bit. So if you immediately
  * begin trying to poll for the state, you may fall right out of your
  * loop without any of the correction calculations having taken place.
  * The recommendation from the hardware team is to wait till ECC_STATE
  * reads less than 4, which means ECC HW has entered correction state.
  */
 do {
  ecc_state = (davinci_nand_readl(info,
    NANDFSR_OFFSET) >> 8) & 0x0f;
  cpu_relax();
 } while (ecc_state < 4);

 

They are totally different.  I think the first one is wrong and the second one is right.

Could somebody please help to tell me which one is the right one?

 

Thanks and Best Regards,

Ivy

  • 0
    Intellectual 730 points

    Hi,

    I tried to modify Linux 2.6.1 kernel cod to the second way, it failed to correct ECC error.

    Why it did work in UBL but not in Kernel?

    I will try Uboot later.

     

    Thanks and Best Regards,

    Ivy

     

  • 0 in reply to Ivy Liu
    Guru 31670 points

    Ivy,

    There are many such issues in general with NAND driver of Davinci. But the general idea is that you've to use the same algorithm which is used for writing as well as reading. If you are writing using u-boot and reading from kernel, the ECC values and offsets in the spare area has to match. 

  • 0 in reply to Renjith Thomas
    Intellectual 730 points

    Hi Renjith,

    Thank you very much for your reply.

    Yes I am using same ECC layout in Uboot and kernel.

    The problem is when there are some 1-4 bit ecc errors in NAD Flash, sometimes the correction algrithm in Kernel can not fix it. 

     

    Thanks and Best Regards,

    Ivy

  • 0 in reply to Ivy Liu
    Guru 15510 points

    Hi Renjith and lvy,

    I'm sorry interrupting you.
    I have a question about 4-bit ECC correction.

    I understand about ECC correction as follow but is it correct?
    1.UBL will process 4-bit ECC correction during the u-boot transfer from NAND to DDR.
      Actually, ECC detection is done by AEMIF hardware and correction is done by SW.

    2.With default setting of Linux SDK, 4-bit ECC correction will be processed anytime if there are access to NAND.
    3.Each RBL, UBL, U-boot, and Kernel have ECC correction algorithm.

    best regards,
    g.f.

  • 0 in reply to g.f.
    Guru 31670 points

    GF,

    g.f. said:

    1.UBL will process 4-bit ECC correction during the u-boot transfer from NAND to DDR.
      Actually, ECC detection is done by AEMIF hardware and correction is done by SW.

    2.With default setting of Linux SDK, 4-bit ECC correction will be processed anytime if there are access to NAND.
    3.Each RBL, UBL, U-boot, and Kernel have ECC correction algorithm.

    Your understanding is correct.

  • 0 in reply to g.f.
    Intellectual 730 points

    Hi g.f.

    1)  By default, the UBL ,U-boot and Linux Kernel source code you got from TI are using 4-bit H/W ECC correction and both ECC detection and Correction are done by hardware, not software. You can change it if you want to use software ECC.

    2)  ECC correction only will be processed when you asked. That means if you want to do H/W ECC correction, you have to enable H/W ECC every time before reading( this is already done in software, you do not need to worry about it). Please see the source code below,

      chip->ecc.hwctl(mtd, NAND_ECC_READ);
      chip->read_buf(mtd, p, eccsize);

    Sometimes, you do not need to do ECC correction when accessing NAND Flash, for example, getting raw data,  getting the OOB data, or getting the BBT.

    3)  You are right, all of them have their own ECC correction algorithm. But the 4-bit H/W ECC correction algorithm in old version UBL has bug and can not correct ECC errors, please make sure that you put the patch in.  

    Ivy

  • 0 in reply to Ivy Liu
    Guru 15510 points

    Hi Renjith and lvy,

    Thank you so much.
    I know undstand about ECC.

    best regard,
    g.f.

  • 0 in reply to g.f.
    Guru 20755 points
    Hello,

    I know it is old thread but for understanding the ecc in dm365:
    Is it that the newer kernel (2.6.32) is doing the ecc correction better than 2.6.18 ?

    Regards,
    Ran
  • 0 in reply to ranchu
    Intellectual 730 points
    Hi Ran,

    Yes. linux kernel 2.6.32 had fixed the ecc correction bug which 2.6.18 has.

    Best Regards,
    Ivy