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DM368 8K page size NAND support

Hi,


I'm working with a custom board that relies on a DM368 processor and I'm currently trying to add support for a 29F64G08CBAAA Micron NAND chip. According to the datasheet, it has a 8K + 448 bytes page size. I checked and the silicon revision of the processor I'm using is 1.2 and it is supposed to support such page size (even when they mention that at the time of writing of the technical documents, there were no available NAND pieces to test the RBL support for this page size).


My question is, where can I find the ECC layout for a 8K page size so that I can start adding the support in the bootloader and kernel?


Any help is much appreciated.

Thanks

Diego Chaverri

  • Hi Diego,

    Refer the below websites

    http://processors.wiki.ti.com/index.php/DM365_Nand_ECC_layout

    http://davinci-ipnc.blogspot.in/2012/02/dm368ipnc-nand-ecc-issue-ecc-layout.html

    http://davinci-ipnc.blogspot.in/

    http://u-boot.10912.n7.nabble.com/PATCH-2-3-mtd-ifc-Add-support-of-8K-page-size-NAND-flash-td163868.html

  • Hi Titus,


    Thanks for your answer, but still remains my question on what should be the ECC layout to use for a 8K page (what ECC byte positions, free positions). I haven't found just yet any reference from TI regarding this.

    The links you posted have some info on how to fix the issue with a 2K page size NAND (mismatch between standard ECC layout and the one recognized by the RBL) but I'm still looking for a reference on what should be the layout for 8K.



    Thank you

    Diego

  • Hi Diego,

    Whether your processor is supporting 8K page NAND in RBL code which is listed by TI?

  • Hi Titus, 

    I really appreciate your help, I've been having lots of trouble finding a light at the end of the tunnel on this matter.

    I'm pretty sure that it is likely the case that my NAND chip, Micron 29F64G08CBAAA, is not supported by default by the RBL.

    I found this link 

    http://processors.wiki.ti.com/index.php/List_of_NANDs_devices_supported_by_TI_RBLs

    I'm not sure how old this link is though.

    Either way my confusion remains the same:

    1) If my NAND chip is not listed, is it possible to have a software workaround (I assume it would be at UBL level) to recognize my chip?

    My guess is that probably the RBL in my DM368 silicon revision does support 8K page size NAND chips but I have not found any reference to this. 

    I found this silicon revision for DM355/DM335 which are much older processors than the DM368, I would assume then that 8K should then be available for DM368 latest silicon revisions' RBL as well but as I said I have no reference to confirm this.

    http://www.ti.com/lit/an/spraba1b/spraba1b.pdf

    2) If 8K page size is supported, how do I know about the ECC layout I should use? I know TI uses a custom ECC layout with their platforms but the wiki pages like the one you previously provided only refers to the layout for 2K page size NAND pieces.

    Thanks a lot for your help Titus

    Diego Chaverri 

  • Hi Diego,

    1) If my NAND chip is not listed, is it possible to have a software workaround (I assume it would be at UBL level) to recognize my chip?

    My guess is that probably the RBL in my DM368 silicon revision does support 8K page size NAND chips but I have not found any reference to this. 

    I found this silicon revision for DM355/DM335 which are much older processors than the DM368, I would assume then that 8K should then be available for DM368 latest silicon revisions' RBL as well but as I said I have no reference to confirm this.

    Technically speaking,

    Suppose, If RBL is not supporting the 8KB page NAND then RBL could not find your NAND to get/read the UBL code to proceed to next step right!

    Check it out Errata doc for DM368

    http://www.ti.com/lit/er/sprz316b/sprz316b.pdf

    Refer RBL NAND boot in DM368 Data Sheet

    • ARM ROM Boot - NAND Mode
    – No support for a full firmware boot. Instead, copies a second stage user boot loader (UBL) from
    NAND flash to ARM internal RAM (AIM) and transfers control to the user-defined UBL.
    – Support for NAND with page sizes up to 4096 bytes.
    – Support for magic number error detection and retry (up to 24 times) when loading UBL
    – Support for up to 30KB UBL (32KB IRAM - ~2KB for RBL stack)
    – Optional, user-selectable, support for use of DMA and I-cache during RBL execution (i.e.,while
    loading UBL)
    – Supports booting from 8-bit NAND devices (16-bit NAND devices are not supported)
    – Uses/Requires 4-bit HW ECC (NAND devices with ECC requirements ≤ 4 bits per 512 bytes are
    supported)
    – Supports NAND flash that requires chip select to stay low during the tR read time

    Nice investigation Diego,