Hi experts,
DM36x UBL in IPNC RDK has following codes.
----------------- from device.c-----------------------------------
Uint32 DEVICE_PLL2Init()
{
……..
UTIL_waitLoop(150);
/*Wait for PLL to LOCK */
while(! (((SYSTEM->PLL1_CONFIG) & 0x07000000) == 0x07000000));
UTIL_waitLoop(4100);
return E_PASS;
}
BTW, ARM subsystem User’s guide says that bit[27:25] indicates the LOCK status. If it’s correct, then upper code should use 0x0E000000. Which one is correct?
PLLC2_CONFIG
bit 27-25 : 111b=locked
bit 24 : reserved
I have another question.
DEVICE_init has following sequence. I woner why PLL2init is called before PLL1init.
The user guide has following description. Currently, the PERI_CLKCTL.ARMCLKS is set on the PLL2init. So I think PLL1init -> PLL2init sequence is correct.. But the latest RDK has reverse order(older DVSDK has PLL1init ->PLL2init order).
-------------------------- from user guide---------------------------
NOTE: If ARM926 needs to be run from PLLC2SYSCLK2, then set the PERI_CLKCTL.ARMCLKS
bit to 1 after the PLLC1 and PLLC2 configuration is completed.
Uint32 DEVICE_init()
{
...........
// DDR PLL setup
if (status == E_PASS) status |= DEVICE_PLL2Init();
// System PLL setup
if (status == E_PASS) status |= DEVICE_PLL1Init();
// DDR2 module setup
if (status == E_PASS) status |= DEVICE_DDR2Init();
#endif
// AEMIF Setup
if (status == E_PASS) status |= DEVICE_EMIFInit();
.....
}
Thanks,
Devin