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DM355 sleep and wake-up control

TETSUOMA
Prodigy 210 points

Hello,

We are planning to control the sleep and wake-up of DM355 using "Sleep.s" which we had downloaded at  the following URL and having encountered a problem.

https://git.kernel.org/cgit/linux/kernel/git/nsekhar/linux-davinci.git/tree/arch/arm/mach-davinci

When we comment out the following two lines,  we sometimes encounter the wake-up failure.

     /* Disable DDR2 LPSC */
     /* Enable DDR2 LPSC */

We guess that the above two lines include the reset of "DDR controller" using "davinci_ddr_psc_config".

Do we need to reset the DDR controller during the wake-up process?

We would like to clarify the reason of the problem and your help would be greatly appreciated.

Thanks,

  • 0
    Prodigy 210 points

    Sorry for my self follow-up.

    Our team has proceeded with the testing some more.

    After returning from the sleep state, we set MDCTL as "SyncReset state(0x1)" , then "Enable state(0x3)".

    After the above procedure, we seem to be able to access DDR2 correctly.

    Does anyone know whether we need to "reset"  the DDR2 controller after returning from the sleep state?

    I'd appreciate any suggestions.

    Regards,

    MDCTLへセットするビットをSyncReset state(0x1)→Enable state(0x3)とすると
    正常にアクセスできるようになりました。