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SPI0 of DM385 not working

HanGil Kang
Prodigy 130 points
Other Parts Discussed in Thread: DM385, SYSCONFIG

Hi. I am trying to use SPI0 module in DM385 but it is not working. I followed procedure mentioned in Technical Reference Manual(DM385) and here is the brief explanation how I did it.

Register Set
SPI0_BASE_ADDR at 0x48030000u
Enabled clock by CM_ALWON_SPI_CLKCTRL register

Initialization
1. SPI CLK Enable 2. MCSPI_SYSCONFIG SOFTRESET 3. MCSPI_SYSSTATUS wait reset completed
4. MCSPI_CH0CONF set 5. McSPI_MODULCTRL set 6. MCSPI_IRQSTATUS set 

Send SPI signals
1. MCSPI_CH0CTRL Channel 0 enable 2. MCSPI_TX0 write data 3. MCSPI_CH0STAT wait until end of transfer
4. MCSPI_CH0CTRL Channel 0 disable 
 
Though I followed all steps above, I have not been able to see the proper data source from oscilloscope and due to the reason, IMX172 sensor connected to our board does not work. As the situation I am facing, I request you to give me advices. I attached source code down below. Thank you in advance.
void Iss_Imx172HWSPIInit()
{
	Vps_printf("HW SPI Init!\n");
	*(volatile UInt32*)(0x48181590) = 0x2; // SPI CLK Enable
	Vps_printf("HW SPI CLK Enabled!\n");

	*(volatile UInt32*)(SPI0_BASE_ADDR + 0x110) |= (0x1<<1); // MCSPI_SYSCONFIG SOFTRESET
	while(((*(volatile UInt32*)(SPI0_BASE_ADDR + 0x110))&(0x1<<1))==1) {;} // wait softreset done
	Vps_printf("HW SPI softreset done!\n");
	while((*(volatile UInt32*)(SPI0_BASE_ADDR + 0x114))==0) {;} // MCSPI_SYSSTATUS wait reset completed
	Vps_printf("HW SPI reset completed!\n");

	*(volatile UInt32*)(SPI0_BASE_ADDR + 0x12C) |= (0x1<<13); // TRM 2h
	*(volatile UInt32*)(SPI0_BASE_ADDR + 0x12C) |= (0x1<<7) | (0x1<<8) | (0x1<<9); // WL 7h
	*(volatile UInt32*)(SPI0_BASE_ADDR + 0x128) = 0x1; // McSPI_MODULCTRL
	
	*(volatile UInt32*)(SPI0_BASE_ADDR + 0x12C) |= (0x1<<6); // EPOL 1h
	*(volatile UInt32*)(SPI0_BASE_ADDR + 0x12C) |= (0x1<<1); // POL 1h
	*(volatile UInt32*)(SPI0_BASE_ADDR + 0x12C) |= (0x1); // PHA 1h


	*(volatile UInt32*)(SPI0_BASE_ADDR + 0x12C) |= (0x1<<24) // SBPOL 1h
							| (0x1<<25) | (0x1<<26) // TCS 3h
							| (0x1<<29); //CLKG 1h 	

	


	*(volatile UInt32*)(SPI0_BASE_ADDR + 0x118) = (0x0); // MCSPI_IRQSTATUS 0h

	return;
}


void Iss_Imx172HWSPIWrite(UInt16 *regAddr, UInt8 *regValue)
{
	UInt8 upperAddr, lowerAddr;

	lowerAddr = (UInt8)(*regAddr&0xff);
	upperAddr = (UInt8)(*regAddr>>8);

	*(volatile UInt32*)(SPI0_BASE_ADDR + 0x134) = 0x1; // MCSPI_CH0CTRL Channel 0 enable	
	*(volatile UInt32*)(SPI0_BASE_ADDR + 0x138) = IMX172_WRITE_CMD;
	while((*(volatile UInt32*)(SPI0_BASE_ADDR + 0x130))&((0x1<<2)|(0x1<<1))==(0x2<<1)) {;}
	*(volatile UInt32*)(SPI0_BASE_ADDR + 0x134) = 0x0; // MCSPI_CH0CTRL Channel 0 disable
	
	*(volatile UInt32*)(SPI0_BASE_ADDR + 0x134) = 0x1; // MCSPI_CH0CTRL Channel 0 enable
	*(volatile UInt32*)(SPI0_BASE_ADDR + 0x138) = lowerAddr;
	while((*(volatile UInt32*)(SPI0_BASE_ADDR + 0x130))&((0x1<<2)|(0x1<<1))==(0x2<<1)) {;}
	*(volatile UInt32*)(SPI0_BASE_ADDR + 0x134) = 0x0; // MCSPI_CH0CTRL Channel 0 disable
	
	*(volatile UInt32*)(SPI0_BASE_ADDR + 0x134) = 0x1; // MCSPI_CH0CTRL Channel 0 enable
	*(volatile UInt32*)(SPI0_BASE_ADDR + 0x138) = upperAddr;
	while((*(volatile UInt32*)(SPI0_BASE_ADDR + 0x130))&((0x1<<2)|(0x1<<1))==(0x2<<1)) {;}
	*(volatile UInt32*)(SPI0_BASE_ADDR + 0x134) = 0x0; // MCSPI_CH0CTRL Channel 0 disable
	
	*(volatile UInt32*)(SPI0_BASE_ADDR + 0x134) = 0x1; // MCSPI_CH0CTRL Channel 0 enable
	*(volatile UInt32*)(SPI0_BASE_ADDR + 0x138) = regValue;
	while((*(volatile UInt32*)(SPI0_BASE_ADDR + 0x130))&((0x1<<2)|(0x1<<1))==(0x2<<1)) {;}
	*(volatile UInt32*)(SPI0_BASE_ADDR + 0x134) = 0x0; // MCSPI_CH0CTRL Channel 0 disable
	
	return;
}


Best Wishes,

HanGil Kang