DM368 MDIO Connection to Ethernet Switch Device

Daisuke Maeda said:

Our customer wants to access the registers of ethernet switch device via the MDIO interface. The registers are not the standard PHY registers. It need two accesses continuously via the standard MDIO protocol. However the two accesses can be disturbed by the PHY Monitoring.

Can the MDIO interface be used to access the registers? Is there the way to prevent the PHY Monitoring during the two accesses?

You may accesses the registers by enable CONFIG_CMD_MII in u-boot.

Basically, miiphy_write/miiphy_read under uboot are for write/read. you can trace detail about the mapping for each different devices. Then modify the detail inside.

example:

to read a register. you need to write the address first, then read the value

int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data)
{
writel(MDIO_USERACCESS0_GO |

MDIO_USERACCESS0_WRITE_READ |
((reg_num & 0x1f) << 21) |
((phy_addr & 0x1f) << 16),
&adap_mdio->USERACCESS0);

change as below way (you need to modify by yourself in your case)

writel(MDIO_USERACCESS0_GO |

MDIO_USERACCESS0_WRITE_WRITE |
((reg_num & 0x1f) << ??) |
((phy_addr & 0x1f) << ??),
&adap_mdio->USERACCESS0);

writel(MDIO_USERACCESS0_GO |

MDIO_USERACCESS0_WRITE_READ |
((reg_num & 0x1f) << ??) |
((phy_addr & 0x1f) << ??),
&adap_mdio->USERACCESS0);

 ....

}

Hi Merry,

Thank you for your reply.

Can the two accesses be not disturbed by the PHY monitoring?

The most of MDIO implemented in TI processor including DM368 have the PHY monitoring feature so that it is discussed in other post: http://e2e.ti.com/support/arm/sitara_arm/f/791/t/304929.aspx

Best regards,

Daisuke

Daisuke Maeda said:

Can the two accesses be not disturbed by the PHY monitoring?

yes.

example :  davinci_eth_phy_read() was called in multiple place for each function such as below. you may need something like mutex lock/unlock or critical section to protect a complete command... 

static int gen_is_phy_connected(int phy_addr)
{...

return(davinci_eth_phy_read(phy_addr, PHY_PHYIDR1, &dummy));

}

static int gen_get_link_speed(int phy_addr)
{...

if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) && (tmp & 0x04))

...

}

Hi Merry,

Thank you for your reply.

I understand that the PHY monitoring cannot be prevented by something in software because it is operated by the MDIO hardware.

Do I have any misunderstanding?

Best regards,

Daisuke

Hi Merry,

Thank you for your reply.

Yes. "PHY monitoring" means the MDIO interface state machine polls the link status. It is described as follows in TRM.

"Once the MDIO module is enabled, the MDIO interface state machine continuously polls the PHY link status (by reading the generic status register) of all possible 32 PHY addresses and records the results in the MDIO PHY alive status register (ALIVE) and MDIO PHY link status register (LINK). "

Best regards,

Daisuke

As your speaking, PHY monitoring is always working.

That means it should be staggered when user's access.

So check the related kernel's source code as below, and we could find that to make sure PHY could be read/write(__raw_writel/__raw_readl), the PHY state(IDLE) will be confirmed.

static int davinci_mdio_read(struct mii_bus *bus, int phy_id, int phy_reg)

{...

while (1) {

ret = wait_for_user_access(data);
if (ret == -EAGAIN)
continue;
if (ret < 0)
break;

__raw_writel(reg, &data->regs->user[0].access);

ret = wait_for_user_access(data);
if (ret == -EAGAIN)
continue;
if (ret < 0)
break;

reg = __raw_readl(&data->regs->user[0].access);
ret = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -EIO;
break;
}

...

return ret;
}

/* wait until hardware is ready for user access */
static inline int wait_for_user_access(struct davinci_mdio_data *data)
{
struct davinci_mdio_regs __iomem *regs = data->regs;
unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT);
u32 reg;

while (time_after(timeout, jiffies)) {
reg = __raw_readl(&regs->user[0].access);
if ((reg & USERACCESS_GO) == 0)
return 0;

reg = __raw_readl(&regs->control);
if ((reg & CONTROL_IDLE) == 0)
continue;

/*
* An emac soft_reset may have clobbered the mdio controller's
* state machine. We need to reset and retry the current
* operation
*/
dev_warn(data->dev, "resetting idled controller\n");
__davinci_mdio_reset(data);
return -EAGAIN;
}

reg = __raw_readl(&regs->user[0].access);
if ((reg & USERACCESS_GO) == 0)
return 0;

dev_err(data->dev, "timed out waiting for user access\n");
return -ETIMEDOUT;
}

Hi Merry,

Thank you for your reply.

I have known that each user's access is not disturbed by the PHY monitoring. However, the registers in ethernet switch device need two user's accesses continuously. The accesses will be disturbed by the PHY monitoring.

Best regards,

Daisuke

Daisuke Maeda said:

How can the period of PHY monitoring be configured?

> By the following description inside SPRUFI5B.pdf, it should be adjusted.

Once the MDIO state machine has been initialized and enabled, it starts polling all 32 PHY addresses
on the MDIO bus, looking for an active PHY. Since it can take up to 50 ms to read one register, it can
be some time before the MDIO module provides an accurate representation of whether a PHY is
available. A

Hi Merry,

Thank you for your reply. Sorry for my late reply.

Our customer uses I2C which is another interface for the PHY registers.

Best regards,

Daisuke