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Using the wait pin0 of DM385 GPNC NAND in IPNCSDK_3.8.0

JP Park95
Expert 1100 points
Other Parts Discussed in Thread: DM385

Dear All,

I would like to use the  wait pin0 of DM385 GPNC NAND  in IPNCSDK_3.8.0.

SDK : IPNCSDK_3.8.0.

SoC : DM385

NAND : Spansion Nand 2Gbit (Part Number : S34ML02G1)

The DM385 NAND Driver setting  in IPNCSDK_3.8.0 is as below.

IPNCSDK_3.8.0/Source\ti_tools\ipnc_psp_arago/arch/arm/mach-omap2/board-flash.c


static struct omap_nand_platform_data board_nand_data = {
 .nand_setup = NULL,
 .gpmc_t  = &nand_timings,
 .dma_channel = -1,  /* disable DMA in OMAP NAND driver */
 .dev_ready = NULL,
 .bussize        = NAND_OMAP_BUS_8
};

and

/IPNCSDK_3.8.0/Source\ti_tools\ipnc_psp_arago/kernel/drivers/drivers/mtd/nand/omap2.c

 /*
  * If RDY/BSY line is connected to OMAP then use the omap ready
  * funcrtion and the generic nand_wait function which reads the status
  * register after monitoring the RDY/BSY line.Otherwise use a standard
  * chip delay which is slightly more than tR (AC Timing) of the NAND
  * device and read status register until you get a failure or success
  */
 if (pdata->dev_ready) {
  info->nand.dev_ready = omap_dev_ready;
  info->nand.chip_delay = 0;
 } else {
  info->nand.waitfunc = omap_wait;
#ifndef CONFIG_TI8148_EVM_OPTIMIZED
  info->nand.chip_delay = 50;
#else
  info->nand.chip_delay = 22;
#endif
 }

so  delay  function(chip_delay = 50) is excuted when reading data from NAND.

I woud like to use  omap_dev_ready function(wait pin mointering) instead of delay  function(chip_delay = 50).

Do you have patch for  using the  wait pin0(WAIT pin is monitored for read accesses) of DM385 GPNC NAND in IPNCSDK_3.8.0

or

Please let me know how to  read data using the  wait pin0(WAIT pin is monitored for read accesses) of DM385 GPNC NAND in IPNCSDK_3.8.0

highly appreciated.

  • 0 in reply to Pavel Botev
    TI__Guru**** 170625 points

    Note also the below TRM text:

    11.2.4.12.2 NAND Device-Ready Pin

    To avoid a time-out caused by a block/page opening delay in NAND flash, disable the wait pin monitoring for read and write accesses (that is, set the GPMC_CONFIG1_i[[21] WAITWRITEMONITORING and GPMC_CONFIG1_i[[22] WAITREADMONITORING bits to 0, where i = 0 to 5), and use one of the following methods instead:

    • Use software to poll the WAITnSTATUS bit (n = 0 to 1) of the GPMC_STATUS register.

    • Configure an interrupt that is generated on the WAIT signal change (through the GPMC_IRQENABLE[11-8] bits).

    Even if the READWAITMONITORING bit is not set, the external memory nR/B pin status is captured in the programmed WAIT bit in the GPMC_STATUS register.

    The READWAITMONITORING bit method must be used for other memories than NAND flash, if they require the use of a WAIT signal.

    So to use the omap_dev_ready function:

    linux-kernel/arch/arm/mach-omap2/board-flash.c

    -.dev_ready    = NULL,
    +.dev_ready    = (void *) 1,

    linux-kernel/arch/arm/mach-omap2/gpmc-nand.c

    /* Enable RD PIN Monitoring Reg */
        if (gpmc_nand_data->dev_ready) {
            
            //gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_RDY_BSY, 1);
            
        }

    BR
    Pavel