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Interrupt Selection Register Question for DM368 product. RSZ_INT_DMA issues and HSYNC requirements.

Dean73
Prodigy 20 points

In the VPFE manual, sprufg8c.pdf, page 457, section 6.6.5, there is a description for the Interrupt Selection Register.

Table 6-309 has the field descriptions.

For INTSEL3, it says a value of 15 is reserved.  These values are used for INTSEL1 and INTSEL2 in different bit positions.

What does value 15 correspond to?  It is used in the reference code (vpss.c) as the selection for INTSEL2.

  • in reply to mdeneen
    Prodigy 20 points

    Thank you.

    Does RSZ_INT_DMA require a certain "stride" number of HSYNCs to trigger? On some other threads, users report needing extra HSYNCs before getting RSZ_INT_DMA. Please see this thread and post:

    e2e.ti.com/.../1177158

    Another user worked around the non-appearing RSZ_INT_DMA issue by changing to RSZ_INT_LAST_PIX.

    e2e.ti.com/.../806734

    We are not convinced this is the correct approach, however, and would like input from TI Engineers.

    We are using DATA_ENABLE instead of HSYNC as input to the DM368 LV pin. In our system, there are no extra lines or HSYNCs to use as a workaround. We do not want to scale from a smaller number of lines because this creates scaling artifacts.

    Could TI please tell us if extra HSYNCs are in fact required, as reported in the other threads? Is there perhaps a stride requirement (multiple of 16?) to trigger RSZ_INT_DMA?

  • in reply to Dean73
    Intellectual 580 points

    We are now trying to use HSYNC, VSYNC and WEN(DE) but the video data does not appear to be written to SDRAM in this mode, but we are getting interrupts for VSYNC and RSZ_INT_DMA.  We are using the resizer in continuous mode.  We've changed the following VPFE registers SRC_MODE.WRT=1, MODESET.CCDMD=0 and MODESET.SWEN=1.  The SWEN register description has a troubling final sentence:

    External WEN Selection When set to 1 and when ENABLE is set to 1, the external WEN signal is used as the external memory write enable (to SDRAM/DDRAM). The data is stored to memory only when the external sync (HD and VD) signals are active.

    The video source HSYNC and VSYNC are short pulses, and are not active during the active video window.  If the description is accurate, then that explains why no video data is written to SDRAM.  Is there a solution to this?