Hello,
I'm trying to interface the DM368 with an ADV7610, sending a 16 bit YCbCr signal with discrete sync. The image is capture properly (colours are ok), but it is shifted to the bottom right of the screen. I believe this to be due to the delay between H/V sync and valid data coming from the ADV7610, that is indicated by the ADV with a low data enable signal.
It looks like the DM368 is ignoring the low data enable signal going trough the C_WE_FIELD pin, and by dumping the registers configured with the VPFE_YCBCR_SYNC_16 mode it looks like that yes, the VPFE is not aware of the signal and it is ignoring it at the moment.
I've tried to make those changes to suggest to the VPFE to ignore data while the C_WE_FIELD pin is low:
1) Changed the pinmux enabling VIN_CAM_WEN
2) Enabled SWEN (MODESET bit 5)
2) Disabled CCDMD (MODESET bit 7)
3) Enabled FIDMD (CCDCFG bit 6 and 7, can’t understand why a register with two states has two bits)
My MODESET and CCDCFG registers now are 0x1020 and 0x8c0.
However, it looks like I can't see any difference. I also think I found an error in the documentation, either that or I can't read english correctly:
"To enable the filed ID input, bit-5 of the MODESET.SWEN register should be set to interlace mode. To enable the write enable signal, bit-7 of the MODESET.CCDMD register should be set."
While the register map is saying, for bit 7: "CCDMD, Sensor Field Mode. This bit should not be set if the External Write Enable bit is set.", that is what the phrase above says regarding bit 5 instead.
Naturally I tried both options without success. Is there anything else I should set or those few registers are it?
I tried using the BT1120 mode as well, and the image there is centred horizontally, however the vertical axis is still shifted to the bottom of around 20 pixels, and I can't seem to be able to get rid of that.
Thank you,
Giovanni
