Tool/software: Linux
Hi!
In our DM385 design, we are using MIPI CSI interface to camera.
Can you please help me clarify one moment:
For successful csi2_phy_reset; does CSI phy expect LP to HS transition on MIPI clock line or just HS clock presence is enough?
My issue is that when processor MIPI CLK input is connected (by error) to transmitter DATA line, csi2_phy_reset passes OK
(since, I believe, there is LP transition every videoframe and every videoline on DATA lines)
But when connection is made correctly, CLK to CLK, csi2_phy_reset hangs
(as I think because it finds just continuously running HS clock there)
Thanks
