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DM388: Display path for HDDAC and DVO2

Kailash Negi
Intellectual 590 points
Part Number: DM388
Other Parts Discussed in Thread: TVP7002, , DM385, TPS65910, THS7353, THS7360

HI All,

I am trying to create two display link in my usecase one is HDMI and other is HDDAC.

Following is the displayId' s available

DISPLAY_LINK_DISPLAY_BP0:
 DISPLAY_LINK_DISPLAY_BP1:
  DISPLAY_LINK_DISPLAY_SC1:
   DISPLAY_LINK_DISPLAY_SC2:
    DISPLAY_LINK_DISPLAY_SD:

For HDMI display DISPLAY_LINK_DISPLAY_SC2  it is working , but for HDDAC and DVO2 which one we should use, i ve tried with BP0 but i got error that display is already running i have tried with BP1, but i am getting the error while setting the format.

Please clarify on this, below is my code and logs

code:

    CaptureLink_CreateParams    capturePrm;
    DisplayLink_CreateParams    displayPrm;
     DisplayLink_CreateParams displayPrm_SD;

    CaptureLink_VipInstParams *pCaptureInstPrm;
    CaptureLink_OutParams     *pCaptureOutPrm;

    OSA_printf("MultiCh_createVCaptureVDisplayorig\n");
    MultiCh_detectBoard();
    MULTICH_INIT_STRUCT(DisplayLink_CreateParams,displayPrm);
    System_linkControl(SYSTEM_LINK_ID_M3VPSS,
                       SYSTEM_M3VPSS_CMD_RESET_VIDEO_DEVICES,
                       NULL,
                       0,
                       TRUE
                      );

    /*Initialize link IDs*/
    gVcapModuleContext.captureId                = SYSTEM_LINK_ID_CAPTURE;
    gVdisModuleContext.displayId[VDIS_DEV_HDMI] = SYSTEM_LINK_ID_DISPLAY_0;
     gVdisModuleContext.displayId[VDIS_DEV_DVO2] = SYSTEM_LINK_ID_DISPLAY_1;
 
                /*Capture Link params*/
    
                   CaptureLink_CreateParams_Init(&capturePrm);

        capturePrm.numVipInst = 1;//vipInstId;

        capturePrm.outQueParams[0].nextLink = gVdisModuleContext.displayId[VDIS_DEV_HDMI];
                capturePrm.outQueParams[1].nextLink = gVdisModuleContext.displayId[VDIS_DEV_DVO2];
                

        capturePrm.tilerEnable              = FALSE;

        pCaptureInstPrm                     = &capturePrm.vipInst[0];
        pCaptureInstPrm->vipInstId          = SYSTEM_CAPTURE_INST_VIP0_PORTA;//+vipInstId;
        pCaptureInstPrm->videoDecoderId     = SYSTEM_DEVICE_VID_DEC_TVP7002_DRV;
        pCaptureInstPrm->inDataFormat       = SYSTEM_DF_YUV422P;
        pCaptureInstPrm->standard           = SYSTEM_STD_SXGA_60;
                pCaptureInstPrm->numOutput          = 2;

        pCaptureOutPrm                      = &pCaptureInstPrm->outParams[0];
        pCaptureOutPrm->dataFormat          = SYSTEM_DF_YUV420SP_UV; //SYSTEM_DF_RGB24_888
        pCaptureOutPrm->scEnable            = FALSE;
        pCaptureOutPrm->outQueId            = 0;

                pCaptureOutPrm                      = &pCaptureInstPrm->outParams[1];
        pCaptureOutPrm->dataFormat          = SYSTEM_DF_YUV422I_YUYV;
        pCaptureOutPrm->scEnable            = FALSE;
                
        pCaptureOutPrm->outQueId            = 1;


    /*Display link params*/
    MULTICH_INIT_STRUCT(DisplayLink_CreateParams,displayPrm);
    displayPrm.inQueParams[0].prevLinkId = gVcapModuleContext.captureId;
    displayPrm.inQueParams[0].prevLinkQueId = 0;
    displayPrm.displayRes = SYSTEM_STD_1080P_60;
    displayPrm.displayId  = DISPLAY_LINK_DISPLAY_SC2;

    MULTICH_INIT_STRUCT(DisplayLink_CreateParams,displayPrm_SD);
    displayPrm_SD.inQueParams[0].prevLinkId = gVcapModuleContext.captureId;
    displayPrm_SD.inQueParams[0].prevLinkQueId = 1;
    displayPrm_SD.displayRes = SYSTEM_STD_720P_60;
    displayPrm_SD.displayId  = DISPLAY_LINK_DISPLAY_BP1;
     
    /*Create Links*/
    System_linkCreate(gVcapModuleContext.captureId, &capturePrm, sizeof(capturePrm));

    System_linkCreate(gVdisModuleContext.displayId[VDIS_DEV_HDMI], &displayPrm, sizeof(displayPrm));
   
    System_linkCreate(gVdisModuleContext.displayId[VDIS_DEV_DVO2], &displayPrm_SD, sizeof(displayPrm_SD));
    
    MultiCh_memPrintHeapStatus();

logs:

I2C:   ready
DRAM:  1 GiB
DCACHE:  On
NAND:  HW ECC BCH8 Selected
256 MiB
MMC:   OMAP SD/MMC: 0, ON-BOARD SDIO: 1
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@                                                               @@
@@                                                               @@
@@                                                               @@
@@                                                               @@
@@       _______   __       __   ______    ______    ______      @@
@@      /       \ /  \     /  | /      \  /      \  /      \     @@
@@      $$$$$$$  |$$  \   /$$ |/$$$$$$  |/$$$$$$  |/$$$$$$  |    @@
@@      $$ |  $$ |$$$  \ /$$$ |$$ ___$$ |$$ \__$$ |$$ \__$$ |    @@
@@      $$ |  $$ |$$$$  /$$$$ |  /   $$< $$    $$< $$    $$<     @@
@@      $$ |  $$ |$$ $$ $$/$$ | _$$$$$  | $$$$$$  | $$$$$$  |    @@
@@      $$ |__$$ |$$ |$$$/ $$ |/  \__$$ |$$ \__$$ |$$ \__$$ |    @@
@@      $$    $$/ $$ | $/  $$ |$$    $$/ $$    $$/ $$    $$/     @@
@@      $$$$$$$/  $$/      $$/  $$$$$$/   $$$$$$/   $$$$$$/      @@
@@                                                               @@
@@                                                               @@
@@                                                               @@
@@                                                               @@
@@                                                               @@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@

Net:   Ethernet clocking: 0x52
<ethaddr> not set. Reading from E-fuse
Detected MACID:a4:d5:78:d5:4f:4a
cpsw
Hit any key to stop autoboot:  3 2 1 0
reading boot.scr

438 bytes read
Running bootscript from MMC/SD to set the ENV...
## Executing script at 80900000
reading uImage

2500608 bytes read
## Booting kernel from Legacy Image at 81000000 ...
   Image Name:   Linux-2.6.37_DM388_IPNC_3.80.01
   Image Type:   ARM Linux Kernel Image (uncompressed)
   Data Size:    2500544 Bytes = 2.4 MiB
   Load Address: 80008000
   Entry Point:  80008000
   Verifying Checksum ... OK
   Loading Kernel Image ... OK
OK
Using machid 0xf3c from environment

Starting kernel ...

Uncompressing Linux... done, booting the kernel.
Linux version 2.6.37_DM388_IPNC_3.80.01 (anvesha@ubuntu-anvesha) (gcc version 4.5.3 20110311 (prerelease) (GCC) ) #14 Thu Sep 21 11:01:49 IST 2017
CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c53c7f
CPU: VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine: dm385evm
vram size = 4194304 at 0x0
bootconsole [earlycon0] enabled
ti81xx_reserve: ### Reserved DDR region @83500000
reserved size = 4194304 at 0x0
FB: Reserving 4194304 bytes SDRAM for VRAM
Memory policy: ECC disabled, Data cache writeback
OMAP chip is DM385 1.0
SRAM: Mapped pa 0x402f1000 to va 0xfe400000 size: 0xf000
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 12436
Kernel command line: console=ttyO0,115200n8 noinitrd mem=54M rootwait vram=4M notifyk.vpssm3_sva=0xBFD00000 root=/dev/mmcblk0p2 rw eth=00:0C:0C:02:30:FB ip=dhcp cmemk.phys_start=0x83600000 cmemk.phys_end=0x85600000 cmemk.allowOverlap=1 earlyprintk
cpsw: kernel boot params Ethernet address: 00:0C:0C:02:30:FB
PID hash table entries: 256 (order: -2, 1024 bytes)
Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
Memory: 48MB 1MB = 49MB total
Memory: 44264k/44264k available, 11032k reserved, 0K highmem
Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
    DMA     : 0xffc00000 - 0xffe00000   (   2 MB)
    vmalloc : 0xc3800000 - 0xf8000000   ( 840 MB)
    lowmem  : 0xc0000000 - 0xc3600000   (  54 MB)
    pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
    modules : 0xbf000000 - 0xbfe00000   (  14 MB)
      .init : 0xc0008000 - 0xc0040000   ( 224 kB)
      .text : 0xc0040000 - 0xc04c2000   (4616 kB)
      .data : 0xc04c2000 - 0xc0502f80   ( 260 kB)
SLUB: Genslabs=11, HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
NR_IRQS:375
omap_hwmod: gpio1: softreset failed (waited 10000 usec)
omap_hwmod: gpio2: softreset failed (waited 10000 usec)
omap_hwmod: gpio3: softreset failed (waited 10000 usec)
omap_hwmod: gpio4: softreset failed (waited 10000 usec)
IRQ: Found an INTC at 0xfa200000 (revision 5.0) with 128 interrupts
Total of 128 interrupts on 1 active controller
GPMC revision 6.0
Trying to install interrupt handler for IRQ368
Trying to install interrupt handler for IRQ369
Trying to install interrupt handler for IRQ370
Trying to install interrupt handler for IRQ371
Trying to install interrupt handler for IRQ372
Trying to install interrupt handler for IRQ373
Trying to install interrupt handler for IRQ374
Trying to install type control for IRQ375
Trying to set irq flags for IRQ375
OMAP clockevent source: GPTIMER1 at 20000000 Hz
Console: colour dummy device 80x30
Calibrating delay loop... 599.65 BogoMIPS (lpj=2998272)
pid_max: default: 32768 minimum: 301
Security Framework initialized
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
devtmpfs: initialized
TI81XX: Map 0x83500000 to 0xfe500000 for dram barrier
TI81XX: Map 0x40300000 to 0xfe600000 for sram barrier
omap_voltage_early_init: voltage driver support not added
regulator: core version 0.5
regulator: dummy:
NET: Registered protocol family 16
omap_voltage_domain_lookup: Voltage driver init not yet happened.Faulting!
omap_voltage_add_dev: VDD specified does not exist!
OMAP GPIO hardware version 0.1
OMAP GPIO hardware version 0.1
OMAP GPIO hardware version 0.1
OMAP GPIO hardware version 0.1
omap_mux_init: Add partition: #1: core, flags: 4
Cannot clk_get ck_32
Debugfs: Only enabling/disabling deep sleep and wakeup timer is supported now
registered ti81xx_vpss device
registered ti81xx_vidout device
registered ti81xx on-chip HDMI device
registered ti81xx_fb device
bio: create slab <bio-0> at 0
SCSI subsystem initialized
USBSS revision 4ea2080b
registerd cppi-dma Intr @ IRQ 17
Cppi41 Init Done
omap_i2c omap_i2c.1: bus 1 rev4.0 at 100 kHz
regulator: VRTC: 1800 mV
regulator: VIO: 1500 mV
regulator: VDD1: 600 <--> 1500 mV at 1200 mV
regulator: VDD2: 600 <--> 1500 mV at 1200 mV
regulator: VDDCTRL: 600 <--> 1400 mV at 1200 mV
regulator: LDO1: 1100 <--> 3300 mV at 1800 mV
regulator: LDO2: 1100 <--> 3300 mV at 1800 mV
regulator: LDO3: 1100 <--> 3300 mV at 3300 mV
regulator: LDO4: 1100 <--> 3300 mV at 1800 mV
regulator: LDO5: 1100 <--> 3300 mV at 3300 mV
regulator: LDO6: 1100 <--> 3300 mV at 3300 mV
regulator: LDO7: 1100 <--> 3300 mV at 3300 mV
regulator: LDO8: 1100 <--> 3300 mV at 1800 mV
tps65911-rtc tps65911-rtc: rtc core: registered tps65911-rtc as rtc0
tps65910 1-002d: No interrupt support, no core IRQ
Advanced Linux Sound Architecture Driver Version 1.0.23.
Switching to clocksource gp timer
musb-hdrc: version 6.0, peripheral, debug=0
musb-hdrc musb-hdrc.0: dma type: dma-cppi41
MUSB controller-0 revision 4ea20800
usb2phy: computed values rxcalib(15)DACs(21 12 14)
usb2phy: override computed values rxcalib(15)DACs(21 12 14)
usb2phy_config: musb(0) rxcalib done, rxcalib read value 6f6ad976
musb-hdrc musb-hdrc.0: USB Peripheral mode controller at c381e000 using DMA, IRQ 18
NET: Registered protocol family 2
IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
TCP established hash table entries: 2048 (order: 2, 16384 bytes)
TCP bind hash table entries: 2048 (order: 1, 8192 bytes)
TCP: Hash tables configured (established 2048 bind 2048)
TCP reno registered
UDP hash table entries: 256 (order: 0, 4096 bytes)
UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
NET: Registered protocol family 1
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
NetWinder Floating Point Emulator V0.97 (double precision)
PMU: registered new PMU device of type 0
omap-iommu omap-iommu.0: ducati registered
omap-iommu omap-iommu.1: sys registered
JFFS2 version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
msgmni has been set to 86
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
CMEMK module: built on Sep 12 2017 at 11:45:41
  Reference Linux version 2.6.37
  File /home/anvesha/DM388/ipnc_3.8/Source/ti_tools/linuxutils_3_23_00_01/packages/ti/sdo/linuxutils/cmem/src/module/cmemk.c
allocated heap buffer 0xc5000000 of size 0x2000000
cmemk initialized
Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
omap_uart.0: ttyO0 at MMIO 0x48020000 (irq = 72) is a OMAP UART0
console [ttyO0] enabled, bootconsole disabled
console [ttyO0] enabled, bootconsole disabled
omap_uart.1: ttyO1 at MMIO 0x48022000 (irq = 73) is a OMAP UART1
omap_uart.2: ttyO2 at MMIO 0x48024000 (irq = 74) is a OMAP UART2
brd: module loaded
loop: module loaded
omap2-nand driver initializing
ONFI param page 0 valid
ONFI flash detected
NAND device: Manufacturer ID: 0x2c, Chip ID: 0xca (Micron NAND 256MiB 3,3V 16-bit)
omap2-nand: detected x16 NAND flash
Creating 8 MTD partitions on "omap2-nand.0":
0x000000000000-0x000000020000 : "U-Boot-min"
0x000000020000-0x000000260000 : "U-Boot"
0x000000260000-0x000000280000 : "U-Boot Env"
0x000000280000-0x0000006c0000 : "Kernel"
0x0000006c0000-0x000006fc0000 : "File System"
0x000006fc0000-0x000007bc0000 : "Data"
0x000007bc0000-0x00000b0c0000 : "File System2"
0x00000b0c0000-0x000010000000 : "Reserved"
davinci_mdio davinci_mdio.0: davinci mdio revision 1.6
davinci_mdio davinci_mdio.0: detected phy mask fffffffc
davinci_mdio.0: probed
davinci_mdio davinci_mdio.0: phy[0]: device 0:00, driver unknown
davinci_mdio davinci_mdio.0: phy[1]: device 0:01, driver unknown
g_mass_storage gadget: Mass Storage Function, version: 2009/09/11
g_mass_storage gadget: Number of LUNs=1
 lun0: LUN: removable file: (no medium)
g_mass_storage gadget: Mass Storage Gadget, version: 2009/09/11
g_mass_storage gadget: userspace failed to provide iSerialNumber
g_mass_storage gadget: g_mass_storage ready
mice: PS/2 mouse device common for all mice
i2c /dev entries driver
Linux video capture interface: v2.00
OMAP Watchdog Timer Rev 0x00: initial timeout 60 sec
notify_shm_drv: no DSP present (MULTIPROC_INVALIDID)
notify_init : notify drivercreated  for  remote proc id 1 at physical Address 0xbfd00000
cm: Module associated with clock hdmi_i2s_fck didn't enable in 100000 tries
asoc: tlv320aic3x-hifi <-> davinci-mcasp.1 mapping ok
asoc: HDMI-DAI-CODEC <-> hdmi-dai mapping ok
ALSA device list:
  #0: TI81XX EVM
nf_conntrack version 0.5.0 (691 buckets, 2764 max)
ip_tables: (C) 2000-2006 Netfilter Core Team
TCP cubic registered
NET: Registered protocol family 17
Bridge firewalling registered
lib80211: common routines for IEEE802.11 drivers
Registering the dns_resolver key type
VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
omap_voltage_late_init: Voltage driver support not added
Power Management for TI81XX.
Detected MACID=0:c:c:2:30:fb
tps65911-rtc tps65911-rtc: setting system clock to 2000-01-01 00:00:00 UTC (946684800)
mmc1: new high speed SDHC card at address aaaa
mmcblk0: mmc1:aaaa SS08G 7.40 GiB
 mmcblk0: p1 p2

CPSW phy found : id is : 0x4dd074

CPSW phy found : id is : 0x4dd074
Sending DHCP requests .
PHY: 0:01 - Link is Up - 0/Half
PHY: 0:01 - Link is Down
PHY: 0:01 - Link is Up - 100/Half
., OK
IP-Config: Got DHCP answer from 0.0.0.0, my address is 192.168.1.2
IP-Config: Complete:
     device=eth0, addr=192.168.1.2, mask=255.255.255.0, gw=192.168.1.1,
     host=192.168.1.2, domain=, nis-domain=(none),
     bootserver=0.0.0.0, rootserver=0.0.0.0, rootpath=
EXT3-fs: barriers not enabled
kjournald starting.  Commit interval 5 seconds
EXT3-fs (mmcblk0p2): warning: mounting fs with errors, running e2fsck is recommended
EXT3-fs (mmcblk0p2): using internal journal
EXT3-fs (mmcblk0p2): mounted filesystem with writeback data mode
VFS: Mounted root (ext3 filesystem) on device 179:2.
devtmpfs: mounted
Freeing init memory: 224K
INIT: version 2.86 booting
Please wait: booting...
Starting udev
WARNING: -e needs -E or -F
Remounting root file system...
Caching udev devnodes
root: mount: mounting /dev/root on / failed: No such file or directory
Configuring network interfaces... udhcpc (v1.13.2) started
Sending discover...
Sending select for 192.168.1.2...
Lease of 192.168.1.2 obtained, lease time 86400
adding dns 192.168.1.1
done.
Setting up IP spoofing protection: rp_filter.
rm: cannot remove '/tmp': Device or resource busy
Fri Nov  9 12:48:00 GMT-8 2012
 inside finish.sh
UBI: attaching mtd5 to ubi0
UBI: physical eraseblock size:   131072 bytes (128 KiB)
UBI: logical eraseblock size:    126976 bytes
UBI: smallest flash I/O unit:    2048
UBI: sub-page size:              512
UBI: VID header offset:          2048 (aligned 2048)
UBI: data offset:                4096
UBI: max. sequence number:       2284
UBI: attached mtd5 to ubi0
UBI: MTD device name:            "Data"
UBI: MTD device size:            12 MiB
UBI: number of good PEBs:        96
UBI: number of bad PEBs:         0
UBI: number of corrupted PEBs:   0
UBI: max. allowed volumes:       128
UBI: wear-leveling threshold:    4096
UBI: number of internal volumes: 1
UBI: number of user volumes:     1
UBI: available PEBs:             0
UBI: total number of reserved PEBs: 96
UBI: number of PEBs reserved for bad PEB handling: 2
UBI: max/mean erase counter: 27/24
UBI: image sequence number:  -776408747
UBI: background thread "ubi_bgt0d" started, PID 304
UBI device number 0, total 96 LEBs (12189696 bytes, 11.6 MiB), available 0 LEBs (0 bytes), LEB size 126976 bytes (124.0 KiB)
UBIFS: recovery needed
UBIFS: recovery completed
UBIFS: mounted UBI device 0, volume 0, name "ubifs_volume"
UBIFS: file system size:   10285056 bytes (10044 KiB, 9 MiB, 81 LEBs)
UBIFS: journal size:       1015809 bytes (992 KiB, 0 MiB, 6 LEBs)
UBIFS: media format:       w4/r0 (latest is w4/r0)
UBIFS: default compressor: lzo
UBIFS: reserved for root:  485787 bytes (474 KiB)
UBI: attaching mtd7 to ubi1
UBI: physical eraseblock size:   131072 bytes (128 KiB)
UBI: logical eraseblock size:    126976 bytes
UBI: smallest flash I/O unit:    2048
UBI: sub-page size:              512
UBI: VID header offset:          2048 (aligned 2048)
UBI: data offset:                4096
UBI: max. sequence number:       331
UBI: attached mtd7 to ubi1
UBI: MTD device name:            "Reserved"
UBI: MTD device size:            79 MiB
UBI: number of good PEBs:        634
UBI: number of bad PEBs:         0
UBI: number of corrupted PEBs:   0
UBI: max. allowed volumes:       128
UBI: wear-leveling threshold:    4096
UBI: number of internal volumes: 1
UBI: number of user volumes:     1
UBI: available PEBs:             0
UBI: total number of reserved PEBs: 634
UBI: number of PEBs reserved for bad PEB handling: 6
UBI: max/mean erase counter: 23/12
UBI: image sequence number:  1352455207
UBI: background thread "ubi_bgt1d" started, PID 316
UBI device number 1, total 634 LEBs (80502784 bytes, 76.8 MiB), available 0 LEBs (0 bytes), LEB size 126976 bytes (124.0 KiB)
UBIFS: recovery needed
UBIFS: recovery completed
UBIFS: mounted UBI device 1, volume 0, name "ubifs_volume"
UBIFS: file system size:   78090240 bytes (76260 KiB, 74 MiB, 615 LEBs)
UBIFS: journal size:       3936256 bytes (3844 KiB, 3 MiB, 31 LEBs)
UBIFS: media format:       w4/r0 (latest is w4/r0)
UBIFS: default compressor: lzo
UBIFS: reserved for root:  3688395 bytes (3601 KiB)
numid=1,iface=MIXER,name='PCM Playback Volume'
  ; type=INTEGER,access=rw---R--,values=2,min=0,max=127,step=0
  : values=127,127
  | dBscale-min=-63.50dB,step=0.50dB,mute=0
 [c6xdsp ] Remote Debug Shared Memory @ 0xbff00000
 [m3video] Remote Debug Shared Memory @ 0xbff05020
 [m3vpss ] Remote Debug Shared Memory @ 0xbff0a040
SysLink version : 2.21.02.10
SysLink module created on Date:Sep 12 2017 Time:11:46:04
Trace enabled
Trace SetFailureReason enabled
/dev/mem opened.
             Phy Addr : 0x48181560 Data : 0x00000002
          Unhandled fault: external abort on non-linefetch (0x1018) at 0x4023f0e4
   Phy Addr : 0x48180f10 Data : 0x00000000
             Phy Addr : 0x48180508 Data : 0x00000302
             Phy Addr : 0x48180520 Data : 0x00000002
             Phy Addr : 0x48180524 Data : 0x00000002
             Phy Addr : 0x48180528 Data : 0x00000002
             Phy Addr : 0x4c0000e4 Data : 0x00170209
Bus error

 [host]  Setting DMM priority for [HDVICP0 ] to [1] ( 0x4e000634 = 0x00000009 )

 [host]  Setting L3 bandwidth regulator for [ISS     ] to [press=[3,3] BW=400, WM Cycles=2500]

 [host]  Setting L3 bandwidth regulator for [HDVICP0 ] to [press=[0,0] BW=900, WM Cycles=2500]

 [host]  Setting DMM priority for [ISS     ] to [0] ( 0x4e000634 = 0x00080000 )
Creat queue id:0
queue id:0
FileMngThread created
Creat queue id:32769
queue id:32769
AlramThread created
Share memory init success
Creat queue id:65538
queue id:65538
Creat queue id:98307
queue id:98307
IPNC_3.80.01 (anvesha@ubuntu-anvesha) (gcc version 4.5.3 20110311 (prere
queue id:32769
 [c6xdsp ] Remote Debug Shared Memory @ 0xbff00000
 [m3video] Remote Debug Shared Memory @ 0xbff05020
 [m3vpss ] Remote Debug Shared Memory @ 0xbff0a040

 [host] Attached to slave procId 0.

 [host] Attached to slave procId 1.

 [host] Loaded file ./firmware/ipnc_rdk_fw_m3video.xem3 on slave procId 0.

 [host] Started slave procId 0.

 [host] After Ipc_loadcallback status [0x00000000]

 [host] Loaded file ./firmware/ipnc_rdk_fw_m3vpss.xem3 on slave procId 1.

 [host] Started slave procId 1.

 [host] After Ipc_loadcallback status [0x00000000]
 [m3video] ***** SYSTEM  : Frequency <ORG> - 200000000, <NEW> - 200000000
 [m3video]  
 [m3video]  *** UTILS: CPU KHz = 400000 Khz ***
 [m3video]  
 [m3video]  77: SYSTEM  : System Common Init in progress !!!
 [m3video]  84: SYSTEM: IPC init in progress !!!
 [m3video]  89: SYSTEM: Attaching to [HOST] ...
 [m3video]  143: SYSTEM: Attaching to [HOST] ...

 [host] After Ipc_startcallback status [0x00000000]
 [m3video]  159: SYSTEM: Attaching to [HOST] ... SUCCESS !!!
 [m3vpss ] ***** SYSTEM  : Frequency <ORG> - 200000000, <NEW> - 200000000
 [m3video]  159: SYSTEM: Attaching to [VPSS-M3] ...
 [m3vpss ] notify_attach  rtnVal  0
 [m3vpss ] initProxyServer  rtnVal  0
 [m3vpss ]  
 [m3vpss ]  *** UTILS: CPU KHz = 400000 Khz ***
 [m3vpss ]  
 [m3vpss ]  196: SYSTEM  : System Common Init in progress !!!
 [m3vpss ]  197: SYSTEM: IPC init in progress !!!
 [m3vpss ]  197: SYSTEM: Attaching to [HOST] ...
 [m3video]  209: SYSTEM: Attaching to [VPSS-M3] ...
 [m3vpss ]  246: SYSTEM: Attaching to [HOST] ...
 [m3vpss ]  249: SYSTEM: Attaching to [HOST] ... SUCCESS !!!

 [host] After Ipc_startcallback status [0x00000000]
 [m3video]  259: SYSTEM: Attaching to [VPSS-M3] ...
 [m3vpss ]  249: SYSTEM: Attaching to [VIDEO-M3] ...
 [m3vpss ]  299: SYSTEM: Attaching to [VIDEO-M3] ...
 [m3video]  300: SYSTEM: Attaching to [VPSS-M3] ... SUCCESS !!!
 [m3vpss ]  300: SYSTEM: Attaching to [VIDEO-M3] ... SUCCESS !!!
 [m3video]  300: SYSTEM: Opening MsgQ Heap [IPC_MSGQ_MSG_HEAP] ...
 [m3vpss ]  300: SYSTEM: Creating MsgQ Heap [IPC_MSGQ_MSG_HEAP] ...
 [m3vpss ]  301: SYSTEM: Creating MsgQ [VPSS-M3_MSGQ] ...
 [m3vpss ]  301: SYSTEM: Creating MsgQ [VPSS-M3_ACK_MSGQ] ...
 [m3vpss ]  303: SYSTEM: Notify register to [HOST] line 0, event 12 ...
 [m3vpss ]  303: SYSTEM: Notify register to [VIDEO-M3] line 0, event 12 ...
 [m3vpss ]  304: SYSTEM: IPC init DONE !!!
 [m3vpss ]  319: MEM: Shared Region 2: Base = 0xbb900000, Length = 0x02900000 (41 MB)
 [m3vpss ]  320: MEM: Shared Region 1: Base = 0xbe500000, Length = 0x01500000 (21 MB)
 [m3vpss ] Received character 's'
 [m3vpss ]  322: SYSTEM  : System Common Init Done !!!
 [c6xdsp ] Remote Debug Shared Memory @ 0xbff00000
 [m3video] Remote Debug Shared Memory @ 0xbff05020
 [m3vpss ] Remote Debug Shared Memory @ 0xbff0a040
 [m3video]  400: SYSTEM: Opening MsgQ Heap [IPC_MSGQ_MSG_HEAP] ...
 [m3video]  401: SYSTEM: Creating MsgQ [VIDEO-M3_MSGQ] ...
 [m3video]  401: SYSTEM: Creating MsgQ [VIDEO-M3_ACK_MSGQ] ...
 [m3video]  403: SYSTEM: Notify register to [HOST] line 0, event 12 ...
 [m3video]  403: SYSTEM: Notify register to [VPSS-M3] line 0, event 12 ...
 [m3video]  404: SYSTEM: IPC init DONE !!!
 [m3video]  419: MEM: Shared Region 2: Base = 0xbb900000, Length = 0x02900000 (41 MB)
 [m3video]  419: MEM: Shared Region 1: Base = 0xbe500000, Length = 0x01500000 (21 MB)
 [m3video] Received character 's'
 [m3video]  422: SYSTEM  : System Common Init Done !!!
queue id:65538
Creat queue id:131076
queue id:131076
Can't open /proc/pwm/pwm1:: No such file or directory

CPU is TI812x

*****************************************************************

    IPNC BUILD VERSION: IPNC RDK VERSION 03.80.00.06 (FULL FEATURE)    

*****************************************************************

DEMOCFG Value    : 0
Videocodecmode    : 8
Videocodecres     : 0
streamtype     : 2

 vsenable : 0
./bin/ipnc_rdk_mcfw.out   VNF_QUALITY TRISTREAM TRIPLE_H264 TI2A AEWB 1080P_D1 H264 HIGH_SPEED1 H264 HIGH_SPEED2 MJPEG 80 &

 [host]

 [host]  MultiChannel Framework for IPNC - (c) Texas Instruments 2012

 [host]

 [host]  USAGE: ./ipnc_rdk_mcfw.out <crop_wdth> <crop_height>  <FIT_VERTICAL/FIT_HORIZONTAL>

 [host]

 [host] load enter

 [host] App_loadDemo0

 [host] App_loadDemo else 1
 [c6xdsp ] Remote Debug Shared Memory @ 0xbff00000
 [m3video] Remote Debug Shared Memory @ 0xbff05020
 [m3vpss ] Remote Debug Shared Memory @ 0xbff0a040

 [host] App_loadDemo else 2
ApproDrvInit: 7
Creat queue id:163845
queue id:163845
 [c6xdsp ] Remote Debug Shared Memory @ 0xbff00000
 [m3video] Remote Debug Shared Memory @ 0xbff05020
 [m3vpss ] Remote Debug Shared Memory @ 0xbff0a040

 [host] App_loadDemo else 3

 [host] App_loadDemo else 6
 [c6xdsp ] Remote Debug Shared Memory @ 0xbff00000
 [m3video] Remote Debug Shared Memory @ 0xbff05020
 [m3vpss ] Remote Debug Shared Memory @ 0xbff0a040
 [m3video]  621: SYSTEM  : System Video Init in progress !!!
 [m3vpss ]  622: SYSTEM  : System VPSS Init in progress !!!
 [m3video]  622: SYSTEM: Creating ListMP [VIDEO-M3_IPC_OUT_0] in region 0 ...
 [m3video]  622: SYSTEM: Creating ListMP [VIDEO-M3_IPC_IN_0] in region 0 ...
 [m3video]  623: SYSTEM: ListElem Shared Addr = 0xbe284180
 [m3video]  625: SYSTEM: Creating ListMP [VIDEO-M3_IPC_OUT_1] in region 0 ...
 [m3video]  625: SYSTEM: Creating ListMP [VIDEO-M3_IPC_IN_1] in region 0 ...
 [m3video]  626: SYSTEM: ListElem Shared Addr = 0xbe287680
 [m3video]  636: SYSTEM: Creating ListMP [VIDEO-M3_IPC_OUT_29] in region 0 ...
 [m3video]  636: SYSTEM: Creating ListMP [VIDEO-M3_IPC_IN_29] in region 0 ...
 [m3video]  637: SYSTEM: ListElem Shared Addr = 0xbe28ab80
 [m3vpss ] === I2C0/2 Clk is active ===
 [m3video]  639: SYSTEM: Creating ListMP [VIDEO-M3_IPC_OUT_30] in region 0 ...
 [m3vpss ] PLATFORM: UNKNOWN CPU detected, defaulting to VPS_PLATFORM_CPU_REV_1_0
 [m3video]  639: SYSTEM: Creating ListMP [VIDEO-M3_IPC_IN_30] in region 0 ...
 [m3vpss ]  PLATFORM: UNKNOWN CPU detected, defaulting to ISS_PLATFORM_CPU_REV_2_1
 [m3video]  640: SYSTEM: ListElem Shared Addr = 0xbe2a4800
 [m3vpss ]  642: SYSTEM: Creating ListMP [VPSS-M3_IPC_OUT_0] in region 0 ...
 [m3video]  642: HDVICP: Doing PRCM for IVAHD[0] ...
 [m3vpss ]  642: SYSTEM: Creating ListMP [VPSS-M3_IPC_IN_0] in region 0 ...
 [m3video]  642: HDVICP: PRCM for IVAHD[0] ... DONE.
 [m3vpss ]  643: SYSTEM: ListElem Shared Addr = 0xbe2be480
 [m3video]  644: SYSTEM  : Initializing Links !!!
 [m3vpss ]  645: SYSTEM: Creating ListMP [VPSS-M3_IPC_OUT_1] in region 0 ...
 [m3vpss ]  646: SYSTEM: Creating ListMP [VPSS-M3_IPC_IN_1] in region 0 ...
 [m3video]  644: SYSTEM  : FREE SPACE : System Heap      = 2088976 B, Mbx = 10240 msgs)
 [m3vpss ]  647: SYSTEM: ListElem Shared Addr = 0xbe2c1980
 [m3video]  644: SYSTEM  : FREE SPACE : SR0 Heap         = 2354304 B (2 MB)
 [m3video]  644: SYSTEM  : FREE SPACE : Frame Buffer     = 42991488 B (40 MB)
 [m3vpss ]  661: SYSTEM: Creating ListMP [VPSS-M3_IPC_OUT_24] in region 0 ...
 [m3vpss ]  661: SYSTEM: Creating ListMP [VPSS-M3_IPC_IN_24] in region 0 ...
 [m3video]  645: SYSTEM  : FREE SPACE : Bitstream Buffer = 22019968 B (20 MB)
 [m3vpss ]  661: SYSTEM: ListElem Shared Addr = 0xbe2c4e80
 [m3vpss ]  664: SYSTEM: Creating ListMP [VPSS-M3_IPC_OUT_25] in region 0 ...
 [m3video]  645: SYSTEM: Opening MsgQ [VPSS-M3_MSGQ] ...
 [m3vpss ]  665: SYSTEM: Creating ListMP [VPSS-M3_IPC_IN_25] in region 0 ...
 [m3video]  646: SYSTEM  : FREE SPACE : Tiler Buffer     = 57 B (0 MB)  - TILER OFF
 [m3vpss ]  665: SYSTEM: ListElem Shared Addr = 0xbe2e4880
 [m3video] Entered the MctnfLink_init()
 [m3vpss ]  668: SYSTEM: Creating ListMP [VPSS-M3_IPC_OUT_26] in region 0 ...
 [m3vpss ]  669: SYSTEM: Creating ListMP [VPSS-M3_IPC_IN_26] in region 0 ...
 [m3vpss ]  669: SYSTEM: ListElem Shared Addr = 0xbe304280
 [m3vpss ]  675: SYSTEM: Creating ListMP [VPSS-M3_IPC_OUT_29] in region 0 ...
 [m3vpss ]  676: SYSTEM: Creating ListMP [VPSS-M3_IPC_IN_29] in region 0 ...
 [m3vpss ]  676: SYSTEM: ListElem Shared Addr = 0xbe323c80
 [m3vpss ]  679: SYSTEM: Creating ListMP [VPSS-M3_IPC_OUT_30] in region 0 ...
 [m3vpss ]  679: SYSTEM: Creating ListMP [VPSS-M3_IPC_IN_30] in region 0 ...
 [m3vpss ]  680: SYSTEM: ListElem Shared Addr = 0xbe33d900
 [m3vpss ]  682: SYSTEM : HDVPSS Drivers Version: HDVPSS_01_00_01_37
 [m3vpss ]  682: SYSTEM  : FVID2 Init in progress !!!
 [m3video]  704: SYSTEM  : Initializing Links ... DONE !!!
 [m3video]  704: SYSTEM  : System Video Init Done !!!
 [m3vpss ]  753: SYSTEM  : FVID2 Init in progress DONE !!!
 [m3vpss ]  754: SYSTEM  : Device Init in progress !!!
 [m3vpss ]  Iss_init called !!!!!!
 [m3vpss ]  CPIS_init DONE !!!!!!
 [m3vpss ] initPrms.isI2cInitReq = 1
 [m3vpss ] initPrms.isI2cInitReq = 0
 [m3vpss ]  940: SYSTEM  : Device Init in progress DONE !!!
 [m3vpss ]  993: SYSTEM  : System VPSS Init Done !!!
 [m3vpss ]  994: UTILS: DMA: HWI Create for INT62 !!!
 [m3vpss ]  994: SYSTEM  : Initializing Links !!!
 [m3vpss ]  994: SYSTEM  : FREE SPACE : System Heap      = 1682736 B, Mbx = 10240 msgs)
 [m3vpss ]  994: SYSTEM  : FREE SPACE : SR0 Heap         = 1740928 B (1 MB)
 [m3vpss ]  995: SYSTEM  : FREE SPACE : Frame Buffer     = 38681472 B (36 MB)
 [m3vpss ]  995: SYSTEM  : FREE SPACE : Bitstream Buffer = 22019968 B (20 MB)
 [m3vpss ]  996: SYSTEM  : FREE SPACE : Tiler Buffer     = 57 B (0 MB)  - TILER OFF
 [m3vpss ]  1127: SYSTEM  : Initializing Links ... DONE !!!
 [m3vpss ] Received character 't'

 [host] App_loadDemo else 7
 [c6xdsp ] Remote Debug Shared Memory @ 0xbff00000
 [m3video] Remote Debug Shared Memory @ 0xbff05020
 [m3vpss ] Remote Debug Shared Memory @ 0xbff0a040
 [m3video] Received character 't'

 [host] App_loadDemo else 8

 [host] App_loadDemo10

 [host] App_loadDemo11

 [host] App_loadDemo12

 [host] App_lDMA: Module install successful, device major num = 248
oadDemo13
ERRORDRV: Module install successful
: Module osa_kerDRV: Module built on Sep 26 2017 19:51:08
mod does not exist in /proc/modules

 [host] App_loadDemo14
HDMI W1 rev 4.0
HDMI CEC Spec version 1.2

 [host] App_loadDemo15

 [host]  

 [host]  ORG 0x46c00524: 0

 [host]  NEW 0x46c00524: 2

 [host]  

 [host] App_loadDemo16

 [host] App_loadDemo0

 [host] Application Start Completed

 [host] App_loadDemo_exit

 [host] load exit
rundemo enter

 [host] rundemo enter
App_runDemo()

 [host] App_runDemo()
App_runDemo()1

 [host] App_runDemo()1

 [host]  0: SYSTEM: System Common Init in progress !!!

 [host]  0: SYSTEM: IPC init in progress !!!

 [host]  15: SYSTEM: CPU [DSP] is NOT available on this platform !!!

 [host]  15: SYSTEM: CPU [VIDEO-M3] syslink proc ID is [0] !!!

 [host]  15: SYSTEM: CPU [VPSS-M3] syslink proc ID is [1] !!!

 [host]  15: SYSTEM: CPU [HOST] syslink proc ID is [2] !!!

 [host]  15: SYSTEM: Opening MsgQ Heap [IPC_MSGQ_MSG_HEAP] ...

 [host]  17: SYSTEM: Creating MsgQ [HOST_MSGQ] ...

 [host]  18: SYSTEM: Creating MsgQ [HOST_ACK_MSGQ] ...

 [host]  20: SYSTEM: Opening MsgQ [VIDEO-M3_MSGQ] ...

 [host]  20: SYSTEM: Opening MsgQ [VPSS-M3_MSGQ] ...

 [host]  21: SYSTEM: Notify register to [VIDEO-M3] line 0, event 12 ...

 [host]  22: SYSTEM: Notify register to [VPSS-M3] line 0, event 12 ...

 [host]  23: SYSTEM: IPC init DONE !!!

 [host]  24: SYSTEM: Creating ListMP [HOST_IPC_OUT_29] in region 0 ...

 [host]  26: SYSTEM: Creating ListMP [HOST_IPC_IN_29] in region 0 ...

 [host]  27: SYSTEM: ListElem Shared Addr = 0x40564580

 [host]  28: SYSTEM: Creating ListMP [HOST_IPC_OUT_30] in region 0 ...

 [host]  30: SYSTEM: Creating ListMP [HOST_IPC_IN_30] in region 0 ...

 [host]  32: SYSTEM: ListElem Shared Addr = 0x4057e200

 [host]  34: SYSTEM: Creating ListMP [HOST_IPC_OUT_24] in region 0 ...

 [host]  35: SYSTEM: Creating ListMP [HOST_IPC_IN_24] in region 0 ...

 [host]  37: SYSTEM: ListElem Shared Addr = 0x40597e80

 [host]  38: SYSTEM: Creating ListMP [HOST_IPC_OUT_25] in region 0 ...

 [host]  40: SYSTEM: Creating ListMP [HOST_IPC_IN_25] in region 0 ...

 [host]  41: SYSTEM: ListElem Shared Addr = 0x405b7880

 [host]  43: SYSTEM: Creating ListMP [HOST_IPC_OUT_26] in region 0 ...

 [host]  45: SYSTEM: Creating ListMP [HOST_IPC_IN_26] in region 0 ...

 [host]  46: SYSTEM: ListElem Shared Addr = 0x405d7280

 [host]  47: SYSTEM: System Common Init Done !!!
App_runDemo()2

 [host] App_runDemo()2
App_runDemo()3

 [host] App_runDemo()3
App_runDemo()4

 [host] App_runDemo()4
App_runDemo()5

 [host] App_runDemo()5
App_runDemo()6

 [host] App_runDemo()6

 [host] Before System_linkControl SYSTEM_M3VPSS_CMD_GET_DISPLAYCTRL_INIT
 [m3vpss ] tiedVencs VPS_DC_VENC_HDMI | VPS_DC_VENC_HDCOMP

 [host]  VSYS_USECASE_CAP_DIS0

 [host] MultiCh_createVCaptureVDisplayorig

 [host]  120: MCFW  : CPU Revision [ES1.0] !!!

 [host]  120: MCFW  : Detected [2x SIL1161A, 2x TVP7002 Catalog2x SIL1161A, 2x TVP7002 DVR] Board !!!

 [host]  120: MCFW  : Base Board Revision [REV A] !!!

 [host]  120: MCFW  : Daughter Card Revision [REV A] !!!
 [m3vpss ] VPS_DCTRL_INST_0
 [m3vpss ] IOCTL_VPS_DCTRL_SET_VENC_OUTPUT SYSTEM_DC_VENC_DVO2
 [m3vpss ] IOCTL_VPS_DCTRL_SET_VENC_OUTPUT SYSTEM_DC_VENC_HDMI
 [m3vpss ] IOCTL_VPS_DCTRL_SET_VENC_OUTPUT SYSTEM_DC_VENC_SD
 [m3vpss ] IOCTL_VPS_DCTRL_SET_VENC_OUTPUT SYSTEM_DC_VENC_HDCOMP
 [m3vpss ] IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC VPS_DC_VENC_HDMI | VPS_DC_VENC_HDCOMP
 [m3vpss ] HDCOMPCLK
 [m3vpss ] SYSTEM_M3VPSS_CMD_GET_DISPLAYCTRL_INIT
 [m3vpss ]  2621: CAPTURE: Create in progress !!!
 [m3vpss ]  2659: CAPTURE: VIP0 PortA capture mode is [16-bit, Non-mux Embedded Sync] !!!
 [m3vpss ]  KAILASH Vps_captCreate:228
 [m3vpss ]     TI_8107_BUILD
 [m3vpss ]  3012: CAPTURE: VIP 0: VID DEC 1025 (0x5d): 7002:0002:0000, AUD_STATUS -9
 [m3vpss ] CAPTURE::HEAPID:0    USED:352
 [m3vpss ]  3013: CAPTURE: Create Done !!!
 [m3vpss ]  3548: DISPLAY: Create in progress !!!
 [m3vpss ] DisplayId = 1,DataFormat = 7
 [m3vpss ] SC2 displayInstId = 6
 [m3vpss ]  3549: DISPLAY: Create Done !!!
 [m3vpss ]  3550: DISPLAY: Create in progress !!!
 [m3vpss ] DisplayId = 3,DataFormat = 1
 [m3vpss ] BP1 displayInstId = 1
 [m3vpss ]  KAILASH vpsDdrvSetFmtIoctl:1843
 [m3vpss ]  KAILASH vpsDdrvSetFmtIoctl:1848
 [m3vpss ]  3552: Assertion @ Line: 851 in links_m3vpss/display/displayLink_drv.c: status == FVID2_SOK : failed !!!
INIT:  inside autorun
Entering runlevel: 5
 sbulla: unknown partition table
 sbulla: unknown partition table
Starting telnet daemon.
Starting syslogd/klogd: done

 _____                    _____           _         _   
|  _  |___ ___ ___ ___   |  _  |___ ___  |_|___ ___| |_
|     |  _| .'| . | . |  |   __|  _| . | | | -_|  _|  _|
|__|__|_| |__,|_  |___|  |__|  |_| |___|_| |___|___|_|  
              |___|                    |___|            

Arago Project http://arago-project.org DM385_IPNC ttyO0

Arago 2011.09 DM385_IPNC ttyO0

DM385_IPNC login: root (automatic login)
root@DM385_IPNC:~# mkdosfs 3.0.12 (29 Oct 2011)
unable to get drive geometry, using default 255/63
/dev/sbulla has 255 heads and 63 sectors per track,
logical sector size is 512,
using 0xf8 media descriptor, with 1024 sectors;
file system has 2 12-bit FATs and 4 sectors per cluster.
FAT size is 1 sector, and provides 247 clusters.
There is 1 reserved sector.
Root directory contains 512 slots and uses 32 sectors.
Volume ID is b0fc1bf4, no volume label.
insmod: error inserting 'g_file_storage.ko': -1 No such device
Simple mixer control 'PGA',0
  Capabilities: cvolume cswitch penum
  Capture channels: Front Left - Front Right
  Limits: Capture 0 - 119
  Front Left: Capture 80 [67%] [40.00dB] [on]
  Front Right: Capture 80 [67%] [40.00dB] [on]
queue id:0
./boa: /usr/lib/libssl.so.1.0.0: no version information available (required by ./boa)
./boa: /usr/lib/libcrypto.so.1.0.0: no version information available (required by ./boa)
ApproDrvInit: 3
queue id:163845
queue id:0
TimeOut occure in boot_proc.
Program exit.
TimeOut occure in boot_proc.
Program exit.

thanks

Kailash

  • 0
    TI__Guru**** 398890 points

    Hi Kailash,

    BP paths do not support YUV420 format, so if you want to display YUV420, you need to use either SC1 or SC2 path. Also these paths can be used only if they are not used in the mem2mem operation. 

    Also please include the display paths in the display controller tree. Otherwise it will not allow you to start those paths in the display.

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Intellectual 590 points

    Hi Brijesh,

    Thanks for reply,

    For BP i am setting input standard to SYSTEM_DF_YUV422I_YUYV , Secondly I want to know which path to choose if we want output from DVO2 and HDDAC .

    I didn't understand what is meant by display control tree.

    Are you talking about the code in DisplayLink_drvDisplayCreate where we set instance id based on the path .

       switch (pObj->createArgs.displayId)
        {
            default:
            case DISPLAY_LINK_DISPLAY_AUTO_SELECT:
                pObj->displayInstId = dispId[pObj->tskId -
                                                SYSTEM_LINK_ID_DISPLAY_FIRST];
                pFormat->scanFormat = FVID2_SF_PROGRESSIVE;
                Vps_rprintf("Auto displayInstId = %d\n",pObj->displayInstId);
                break;
            case DISPLAY_LINK_DISPLAY_BP0:
                pObj->displayInstId = VPS_DISP_INST_BP0;
                pFormat->scanFormat = FVID2_SF_PROGRESSIVE;
                Vps_rprintf("BP0 displayInstId = %d\n",pObj->displayInstId);
                break;
            case DISPLAY_LINK_DISPLAY_BP1:
                pObj->displayInstId = VPS_DISP_INST_BP1;
                pFormat->scanFormat = FVID2_SF_PROGRESSIVE;
                Vps_rprintf("BP1 displayInstId = %d\n",pObj->displayInstId);
                break;
            case DISPLAY_LINK_DISPLAY_SC1:
                pObj->displayInstId = DisplayLink_getSc1DispId();
                pFormat->scanFormat = FVID2_SF_PROGRESSIVE;
                Vps_rprintf("SC1 displayInstId = %d\n",pObj->displayInstId);
                break;
            case DISPLAY_LINK_DISPLAY_SC2:
                pObj->displayInstId = DisplayLink_getSc2DispId();
                pFormat->scanFormat = FVID2_SF_PROGRESSIVE;
                Vps_rprintf("SC2 displayInstId = %d\n",pObj->displayInstId);
                break;
            case DISPLAY_LINK_DISPLAY_SD:
                pObj->displayInstId = VPS_DISP_INST_SEC1;
                pFormat->scanFormat = FVID2_SF_INTERLACED;
                Vps_rprintf("SD displayInstId = %d\n",pObj->displayInstId);
                break;
        }

    Thanks

    Kailash

  • 0 in reply to Kailash Negi
    TI__Guru**** 398890 points
    Hi Kailash,


    Path is just one portion, the second portion is path should be connected to the VENC.
    By default, BP0 and BP1 are connected to one of the VENC. You need to check the display controller tree to figure out which path is connected to which venc.
    Once BP paths are connected to the required VENC, it can be displayed on the corresponding VENC.

    Regards,
    Brijesh
  • 0 in reply to Brijesh Jadav
    Intellectual 590 points

    Hi Brijesh,

    I tried searching the code but couldn't figure out how the path is tied up with the encoder and i am new to MCFW. Can you please elaborate where to search for display controller tree in the code.

    I am using EVMDM388 and ipnc 3.8.1 rdk.

    Thanks

    Kailash

  • 0 in reply to Kailash Negi
    Intellectual 590 points
    Hi Brijesh,

    This is the display configuration.
    Vps_DcConfig gSystem_dctrlTriDisplayConfig = {
    VPS_DC_USERSETTINGS, /* Use Case */
    /* Edge information */
    {
    {VPS_DC_BP0_INPUT_PATH, VPS_DC_VCOMP_MUX},
    {VPS_DC_VCOMP_MUX, VPS_DC_VCOMP},
    {VPS_DC_CIG_NON_CONSTRAINED_OUTPUT, VPS_DC_HDMI_BLEND},
    {VPS_DC_CIG_NON_CONSTRAINED_OUTPUT, VPS_DC_HDCOMP_BLEND},
    {VPS_DC_SEC1_INPUT_PATH, VPS_DC_SDVENC_MUX},
    {VPS_DC_SDVENC_MUX, VPS_DC_SDVENC_BLEND},
    {VPS_DC_GRPX0_INPUT_PATH, VPS_DC_HDMI_BLEND},
    {VPS_DC_GRPX0_INPUT_PATH, VPS_DC_HDCOMP_BLEND},
    {VPS_DC_GRPX2_INPUT_PATH, VPS_DC_SDVENC_BLEND},

    {VPS_DC_MAIN_INPUT_PATH, VPS_DC_VCOMP},
    {VPS_DC_AUX_INPUT_PATH, VPS_DC_VCOMP_MUX},
    {VPS_DC_BP1_INPUT_PATH, VPS_DC_SDVENC_MUX},
    },

    12,
    /* VENC information */
    {
    /* Mode information */
    {
    {VPS_DC_VENC_HDMI, {FVID2_STD_1080P_60}
    }
    , /* 1080p30 is mode
    * is overwritten
    * later inside
    * System_displayCtrlInit
    */
    {VPS_DC_VENC_HDCOMP, {FVID2_STD_1080P_60}
    }, /* 1080p30 is mode
    * is overwritten
    * later inside
    * System_displayCtrlInit
    */

    {VPS_DC_VENC_SD, {FVID2_STD_NTSC}
    }
    }
    ,
    (VPS_DC_VENC_HDMI | VPS_DC_VENC_HDCOMP), /* Tied VENC bit
    * mask */
    3u /* Number of VENCs
    */
    }
    };

    Here HDMI and HDCOMP are tied up together , Is this means only one can be used for output?If so then How should i modify it to support output from HDDAC as my VGA connector is connected to HDDAC.

    I ve tried to modify it
    Vps_DcConfig gSystem_dctrlTriDisplayConfig = {
    VPS_DC_USERSETTINGS, /* Use Case */
    /* Edge information */
    {
    {VPS_DC_BP0_INPUT_PATH, VPS_DC_VCOMP_MUX},
    {VPS_DC_VCOMP_MUX, VPS_DC_VCOMP},
    {VPS_DC_CIG_NON_CONSTRAINED_OUTPUT, VPS_DC_HDMI_BLEND},
    {VPS_DC_HDCOMP_MUX, VPS_DC_CIG_PIP_INPUT},
    {VPS_DC_CIG_PIP_OUTPUT, VPS_DC_HDCOMP_BLEND},
    //{VPS_DC_CIG_NON_CONSTRAINED_OUTPUT, VPS_DC_HDCOMP_BLEND},
    {VPS_DC_SEC1_INPUT_PATH, VPS_DC_SDVENC_MUX},
    {VPS_DC_SDVENC_MUX, VPS_DC_SDVENC_BLEND},
    {VPS_DC_GRPX0_INPUT_PATH, VPS_DC_HDMI_BLEND},
    {VPS_DC_GRPX1_INPUT_PATH, VPS_DC_HDCOMP_BLEND},
    {VPS_DC_GRPX2_INPUT_PATH, VPS_DC_SDVENC_BLEND},

    {VPS_DC_MAIN_INPUT_PATH, VPS_DC_HDCOMP_MUX},//VPS_DC_VCOMP},
    {VPS_DC_AUX_INPUT_PATH, VPS_DC_VCOMP_MUX},
    {VPS_DC_BP1_INPUT_PATH, VPS_DC_SDVENC_MUX},
    },

    13,
    /* VENC information */
    {
    /* Mode information */
    {
    {VPS_DC_VENC_HDMI, {FVID2_STD_1080P_60}
    }
    , /* 1080p30 is mode
    * is overwritten
    * later inside
    * System_displayCtrlInit
    */
    {VPS_DC_VENC_HDCOMP, {FVID2_STD_1080P_60}
    }, /* 1080p30 is mode
    * is overwritten
    * later inside
    * System_displayCtrlInit
    */

    {VPS_DC_VENC_SD, {FVID2_STD_NTSC}
    }
    }
    ,
    (VPS_DC_VENC_HDMI | VPS_DC_VENC_HDCOMP), /* Tied VENC bit
    * mask */
    3u /* Number of VENCs
    */
    }
    };
    but its not working.

    Thanks
    Kailash
  • 0 in reply to Kailash Negi
    TI__Guru**** 398890 points
    Hi Kailash,

    In the original Display controller configuration, you already have BP0 patch connected to HDCOMP output, DAC output.
    BP0 -> VCOMP -> HDCOMP Blender.

    so if you just make sure you use BP0 path for the display, it should work.
    Please note the BP0 path only supports YUV422 as input.

    Regards,
    Brijesh
  • 0 in reply to Brijesh Jadav
    Intellectual 590 points
    Hi Brijesh,

    As per the Mapping diagram of TI807 non_constraint_output is connected to DVO2_Blend and HDMI_BLEND, DVO2_blend is connected to HDDAC , But As per the display controller tree code non_constraint_output is directed to HDCOMP_BLEND and HDMI_BLEND.
    We have to refer "Display Controller Macro Mapping - TI8107" or "Display Controller Macro Mapping - TI816X" for DM388EVM?
    For this i have refered "HDVPSS_UserGuide".

    I have tried withe path BP0 the results are dame as SC2 and i can see video on HDMI display connected to HDMI output port , There is no video on the Monitor connected to VGA out port.

    SC2/SC1/BP0 all are showing output on HDMI out.

    note: in the MCFW code 8107_BUILD is enabled and for DM388 EVM.

    As per my requirement i need output to HDMI,HDDAC,SDDAC.

    Thanks
    Kailash
  • 0 in reply to Kailash Negi
    TI__Guru**** 398890 points

    Hi Kailash,

    Oh, i missed that you are using DM388.

    Yes, for DM388, please refer to the Display controller Macro Mapping TI8107. TI8107 is very similar to DM388. 

    Strange that there is no output on VGa connector. are you getting atleast back ground color on the VGA output? Does your monitor or display device detect incoming resolution? If it is not detecting, HDCOMP VENC itself is not on, or there is some module between HDCOMP output and VGA connector which is stopping the signals. 

    I remember there used to be a filter between HDCOMP output and VGA connector. some THS7353. Can you please check if this filter is configured correcty?

    Rgds,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Intellectual 590 points

    Hi Brijesh,

    The module between VGA and HDDAC is THS7360 and it is configuring properly, I have checked it by printing some logs. Below is the display controller code can you please check HDCOMP_VENC configuration is correcte or not.

    Int32 System_displayCtrlInit(VDIS_PARAMS_S * pPrm)
    {

        Int32                   driverRetVal, retVal;
        Vps_DcCreateConfig      dcCreateCfg;
        Vps_CscConfig           dcVcompCscConfig;
        Vps_CscConfig           dcHdcompCscConfig;
        Vps_CscConfig           dcSdCscConfig;
        Vps_DcEdeConfig         dcEdeCfg;
        Vps_DcVencClkSrc        clkSrc;
        Vps_DcConfig            *dctrlTriDisplayConfig = NULL;

    Vps_printf ( " KAILASH common %s:%d\n",__FUNCTION__, __LINE__ );
    #if defined(TI_814X_BUILD)
        /* Need to set this bit only for ti814x to support tied vencs, pin mux settings */
        (* (UInt32 *)0x481C52C8) = 0x01000000;
    #endif

        System_displayUnderflowCheck(TRUE);
    #if defined(TI_814X_BUILD) || defined (TI_8107_BUILD)
        dctrlTriDisplayConfig = &(gSystem_dctrlTriDisplayConfig);
        dctrlTriDisplayConfig->vencInfo.tiedVencs = pPrm->tiedDevicesMask;
    #endif

    #ifdef TI_816X_BUILD
        if(pPrm->tiedDevicesMask == (VPS_DC_VENC_HDMI | VPS_DC_VENC_HDCOMP))
        {
            dctrlTriDisplayConfig = &(gSystem_dctrlTriDisplayConfigHdmi);
            dctrlTriDisplayConfig->vencInfo.tiedVencs = pPrm->tiedDevicesMask;
        }
        if(pPrm->tiedDevicesMask == (VPS_DC_VENC_DVO2 | VPS_DC_VENC_HDCOMP))
        {
            dctrlTriDisplayConfig = &(gSystem_dctrlTriDisplayConfigDvo2);
            dctrlTriDisplayConfig->vencInfo.tiedVencs = pPrm->tiedDevicesMask;
        }
    #endif
        memcpy(&gSystem_objVpss.displayCtrlCfg, dctrlTriDisplayConfig, sizeof(Vps_DcConfig));

        gSystem_objVpss.enableConfigExtVideoEncoder = pPrm->enableConfigExtVideoEncoder;


        retVal = System_configVencInfo(pPrm);
        UTILS_assert(retVal == 0);


        /* Clock VENC_D is always tied to HDMI (DVO1)*/
        gSystem_objVpss.vpllCfg[SYSTEM_VPLL_OUTPUT_VENC_D].outputClk =
                                    System_getClk(pPrm->deviceParams[SYSTEM_DC_VENC_HDMI].resolution);

    #if defined (TI_816X_BUILD) || defined(TI_8107_BUILD)
        if(dctrlTriDisplayConfig->vencInfo.tiedVencs ==
                                          (VPS_DC_VENC_DVO2 | VPS_DC_VENC_HDCOMP)) {
            Vps_rprintf("tiedVencs VPS_DC_VENC_DVO2 | VPS_DC_VENC_HDCOMP\n");
            UTILS_assert (pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].resolution == pPrm->deviceParams[SYSTEM_DC_VENC_HDCOMP].resolution);
                gSystem_objVpss.vpllCfg[SYSTEM_VPLL_OUTPUT_VENC_A].outputClk =
                                         System_getClk(pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].resolution);
         }
        if(dctrlTriDisplayConfig->vencInfo.tiedVencs ==
                                          (VPS_DC_VENC_HDMI | VPS_DC_VENC_HDCOMP)) {
            Vps_rprintf("tiedVencs VPS_DC_VENC_HDMI | VPS_DC_VENC_HDCOMP\n");
            UTILS_assert (pPrm->deviceParams[SYSTEM_DC_VENC_HDMI].resolution == pPrm->deviceParams[SYSTEM_DC_VENC_HDCOMP].resolution);
            gSystem_objVpss.vpllCfg[SYSTEM_VPLL_OUTPUT_VENC_A].outputClk =
                                     System_getClk(pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].resolution);
        }
        if(dctrlTriDisplayConfig->vencInfo.tiedVencs ==
                                          (VPS_DC_VENC_HDMI | VPS_DC_VENC_DVO2)) {
            Vps_rprintf("tiedVencs VPS_DC_VENC_HDMI | VPS_DC_VENC_DVO2\n");                              
            UTILS_assert (pPrm->deviceParams[SYSTEM_DC_VENC_HDMI].resolution == pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].resolution);
            gSystem_objVpss.vpllCfg[SYSTEM_VPLL_OUTPUT_VENC_A].outputClk =
                                     System_getClk(pPrm->deviceParams[SYSTEM_DC_VENC_HDCOMP].resolution);
        }
        if(!(dctrlTriDisplayConfig->vencInfo.tiedVencs)) {
                Vps_rprintf("tiedVencs ##########################\n");
                gSystem_objVpss.vpllCfg[SYSTEM_VPLL_OUTPUT_VENC_A].outputClk =
                                         System_getClk(pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].resolution);
         }
    #endif


        /* Configure pixel clock */
        retVal = System_dispSetPixClk();
        UTILS_assert(FVID2_SOK == retVal);

        dcVcompCscConfig.bypass  =
        dcHdcompCscConfig.bypass =
        dcSdCscConfig.bypass     = FALSE;
        dcVcompCscConfig.coeff   =
        dcHdcompCscConfig.coeff  =
        dcSdCscConfig.coeff      = NULL;

        dcVcompCscConfig.mode  =
        dcHdcompCscConfig.mode =
        dcSdCscConfig.mode     = pPrm->deviceParams[SYSTEM_DC_VENC_HDMI].colorSpaceMode; //VPS_CSC_MODE_HDTV_GRAPHICS_Y2R;

        memset(&dcCreateCfg, 0, sizeof(dcCreateCfg));

        if (pPrm->enableEdgeEnhancement) {
            dcEdeCfg.ltiEnable = TRUE;
            dcEdeCfg.horzPeaking = TRUE;
            dcEdeCfg.ctiEnable = TRUE;
            dcEdeCfg.transAdjustEnable = TRUE;
            dcEdeCfg.lumaPeaking = TRUE;
            dcEdeCfg.chromaPeaking = TRUE;
            dcEdeCfg.minClipLuma = 0;
            dcEdeCfg.maxClipLuma = 1023;
            dcEdeCfg.minClipChroma = 0;
            dcEdeCfg.maxClipChroma = 1023;
            dcEdeCfg.bypass = FALSE;

            dcCreateCfg.edeConfig       = &dcEdeCfg;
        }

        dcCreateCfg.vcompCscConfig  = &dcVcompCscConfig;
        dcCreateCfg.hdcompCscConfig = &dcHdcompCscConfig;
        dcCreateCfg.sdCscConfig     = &dcSdCscConfig;
        Vps_rprintf("VPS_DCTRL_INST_0\n");
        /* Open and configure display controller */
        gSystem_objVpss.fvidDisplayCtrl = FVID2_create(
                          FVID2_VPS_DCTRL_DRV,
                          VPS_DCTRL_INST_0,
                          &dcCreateCfg,
                          &driverRetVal,
                          NULL);
        //GT_assert( GT_DEFAULT_MASK, NULL != gSystem_objVpss.fvidDisplayCtrl );
        UTILS_assert(NULL != gSystem_objVpss.fvidDisplayCtrl);

        /* Set output in display controller */
        if (pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].enable) {
            Vps_rprintf("IOCTL_VPS_DCTRL_SET_VENC_OUTPUT SYSTEM_DC_VENC_DVO2\n");
            retVal = FVID2_control(
                    gSystem_objVpss.fvidDisplayCtrl,
                    IOCTL_VPS_DCTRL_SET_VENC_OUTPUT,
                    &pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].outputInfo,
                    NULL);
            //GT_assert(GT_DEFAULT_MASK, retVal == FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
        }

        if (pPrm->deviceParams[SYSTEM_DC_VENC_HDMI].enable) {
            Vps_rprintf("IOCTL_VPS_DCTRL_SET_VENC_OUTPUT SYSTEM_DC_VENC_HDMI\n");
            retVal = FVID2_control(
                        gSystem_objVpss.fvidDisplayCtrl,
                        IOCTL_VPS_DCTRL_SET_VENC_OUTPUT,
                        &pPrm->deviceParams[SYSTEM_DC_VENC_HDMI].outputInfo,
                        NULL);
            //GT_assert(GT_DEFAULT_MASK, retVal == FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
        }

        if (pPrm->deviceParams[SYSTEM_DC_VENC_SD].enable) {
            Vps_rprintf("IOCTL_VPS_DCTRL_SET_VENC_OUTPUT SYSTEM_DC_VENC_SD\n");
            retVal = FVID2_control(
                        gSystem_objVpss.fvidDisplayCtrl,
                        IOCTL_VPS_DCTRL_SET_VENC_OUTPUT,
                        &pPrm->deviceParams[SYSTEM_DC_VENC_SD].outputInfo,
                        NULL);
            //GT_assert(GT_DEFAULT_MASK, retVal == FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
        }

    #if defined (TI_816X_BUILD) || defined(TI_8107_BUILD)
        if (pPrm->deviceParams[SYSTEM_DC_VENC_HDCOMP].enable) {
            Vps_rprintf("IOCTL_VPS_DCTRL_SET_VENC_OUTPUT SYSTEM_DC_VENC_HDCOMP\n");
            retVal = FVID2_control(
                        gSystem_objVpss.fvidDisplayCtrl,
                        IOCTL_VPS_DCTRL_SET_VENC_OUTPUT,
                        &pPrm->deviceParams[SYSTEM_DC_VENC_HDCOMP].outputInfo,
                        NULL);
            //GT_assert(GT_DEFAULT_MASK, retVal == FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
        }
    #endif

        /* Set the Clock source for VENC_DVO2 */
        if(dctrlTriDisplayConfig->vencInfo.tiedVencs ==
                                          (VPS_DC_VENC_HDMI | VPS_DC_VENC_DVO2)) {
            /* Set the Clock source for DVO2 */
            Vps_rprintf("IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC VPS_DC_VENC_HDMI | VPS_DC_VENC_DVO2\n");
            clkSrc.venc = VPS_DC_VENC_DVO2;
            clkSrc.clkSrc = VPS_DC_CLKSRC_VENCD;
            retVal = FVID2_control(
                         gSystem_objVpss.fvidDisplayCtrl,
                         IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC,
                         &clkSrc,
                         NULL);
            //GT_assert(GT_DEFAULT_MASK, retVal == FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);

            /* Set the Clock source for on-chip HDMI */
            clkSrc.venc = VPS_DC_VENC_HDMI;
            clkSrc.clkSrc = VPS_DC_CLKSRC_VENCD;
            // clkSrc is the same as DVO2 for this App
            retVal = FVID2_control(
                         gSystem_objVpss.fvidDisplayCtrl,
                         IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC,
                         &clkSrc,
                         NULL);
            //GT_assert( GT_DEFAULT_MASK, retVal==FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
    #if defined (TI_816X_BUILD) || defined(TI_8107_BUILD)
    Vps_printf ( " KAILASH %s:%d\n",__FUNCTION__, __LINE__ );
            /* Set the Clock source for HDCOMP */
            clkSrc.venc = VPS_DC_VENC_HDCOMP;
            clkSrc.clkSrc = VPS_DC_CLKSRC_VENCA;
            retVal = FVID2_control(
                         gSystem_objVpss.fvidDisplayCtrl,
                         IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC,
                         &clkSrc,
                         NULL);
            //GT_assert( GT_DEFAULT_MASK, retVal==FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);
    #endif
        }
    #if defined (TI_816X_BUILD) || defined(TI_8107_BUILD)
    Vps_printf ( " KAILASH %s:%d\n",__FUNCTION__, __LINE__ );
        if(dctrlTriDisplayConfig->vencInfo.tiedVencs ==
                                          (VPS_DC_VENC_DVO2 | VPS_DC_VENC_HDCOMP)) {
            Vps_rprintf("IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC VPS_DC_VENC_DVO2 | VPS_DC_VENC_HDCOMP\n");                                  
            /* Set the Clock source for off-chip HDMI */
            clkSrc.venc = VPS_DC_VENC_DVO2;
            clkSrc.clkSrc = VPS_DC_CLKSRC_VENCA;
            // clkSrc is the same as DVO2 for this App
            retVal = FVID2_control(
                         gSystem_objVpss.fvidDisplayCtrl,
                         IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC,
                         &clkSrc,
                         NULL);
            //GT_assert( GT_DEFAULT_MASK, retVal==FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);

            /* Set the Clock source for VGA */
            clkSrc.venc = VPS_DC_VENC_HDCOMP;
            clkSrc.clkSrc = VPS_DC_CLKSRC_VENCA;
            // clkSrc is the same as DVO2 for this App
            retVal = FVID2_control(
                         gSystem_objVpss.fvidDisplayCtrl,
                         IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC,
                         &clkSrc,
                         NULL);
            //GT_assert( GT_DEFAULT_MASK, retVal==FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);

            /* Set the Clock source for on-chip HDMI */
            clkSrc.venc = VPS_DC_VENC_HDMI;
            clkSrc.clkSrc = VPS_DC_CLKSRC_VENCD;
            retVal = FVID2_control(
                         gSystem_objVpss.fvidDisplayCtrl,
                         IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC,
                         &clkSrc,
                         NULL);
            //GT_assert(GT_DEFAULT_MASK, retVal == FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);

        }

        if(dctrlTriDisplayConfig->vencInfo.tiedVencs ==
                                          (VPS_DC_VENC_HDMI | VPS_DC_VENC_HDCOMP)) {
            Vps_rprintf("IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC VPS_DC_VENC_HDMI | VPS_DC_VENC_HDCOMP\n");                              
            /* Set the Clock source for on-chip HDMI */
            clkSrc.venc = VPS_DC_VENC_HDMI;
            clkSrc.clkSrc = VPS_DC_CLKSRC_VENCD;
            // clkSrc is the same as DVO2 for this App
            retVal = FVID2_control(
                         gSystem_objVpss.fvidDisplayCtrl,
                         IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC,
                         &clkSrc,
                         NULL);
            //GT_assert( GT_DEFAULT_MASK, retVal==FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);

            /* Set the Clock source for VGA */
            clkSrc.venc = VPS_DC_VENC_HDCOMP;
            clkSrc.clkSrc = VPS_DC_CLKSRC_VENCD;
            // clkSrc is the same as HDMI for this App
            retVal = FVID2_control(
                         gSystem_objVpss.fvidDisplayCtrl,
                         IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC,
                         &clkSrc,
                         NULL);
            //GT_assert( GT_DEFAULT_MASK, retVal==FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);

            /* Set the Clock source for off-chip HDMI */
            clkSrc.venc = VPS_DC_VENC_DVO2;
            clkSrc.clkSrc = VPS_DC_CLKSRC_VENCA;
            retVal = FVID2_control(
                         gSystem_objVpss.fvidDisplayCtrl,
                         IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC,
                         &clkSrc,
                         NULL);
            //GT_assert(GT_DEFAULT_MASK, retVal == FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);

        }
    Vps_printf ( " KAILASH %s:%d\n",__FUNCTION__, __LINE__ );
    #endif

        if(!(dctrlTriDisplayConfig->vencInfo.tiedVencs)) {
            Vps_rprintf("IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC ###################\n");    
            /* Set the Clock source for off-chip HDMI */
            clkSrc.venc = VPS_DC_VENC_DVO2;
            clkSrc.clkSrc = VPS_DC_CLKSRC_VENCA;
            // clkSrc is the same as DVO2 for this App
            retVal = FVID2_control(
                         gSystem_objVpss.fvidDisplayCtrl,
                         IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC,
                         &clkSrc,
                         NULL);
            //GT_assert( GT_DEFAULT_MASK, retVal==FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);

            /* Set the Clock source for on-chip HDMI */
            clkSrc.venc = VPS_DC_VENC_HDMI;
            clkSrc.clkSrc = VPS_DC_CLKSRC_VENCD;
            retVal = FVID2_control(
                         gSystem_objVpss.fvidDisplayCtrl,
                         IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC,
                         &clkSrc,
                         NULL);
            //GT_assert(GT_DEFAULT_MASK, retVal == FVID2_SOK);
            UTILS_assert(retVal == FVID2_SOK);

        }

        if(pPrm->enableConfigExtThsFilter == TRUE) {
    #if 1//ndef _IPNC_HW_PLATFORM_
    #if 1//def SYSTEM_USE_VIDEO_DECODER
    Vps_printf ( " KAILASH %s:%d\n",__FUNCTION__, __LINE__ );
    Vps_printf ( " KAILASH %s:%d\n",__FUNCTION__, __LINE__ );
            System_Ths7360SfCtrl    thsCtrl;

            /* THS is tied to HDCOMP/HDDAC only for EVM */
            switch (gSystem_objVpss.displayCtrlCfg.vencInfo.modeInfo[1].mInfo.standard)
            {
                case FVID2_STD_720P_60:
                case FVID2_STD_720P_50:
                case FVID2_STD_1080I_60:
                case FVID2_STD_1080I_50:
                case FVID2_STD_1080P_30:
    Vps_printf ( " KAILASH %s:%d\n",__FUNCTION__, __LINE__ );
                    thsCtrl = SYSTEM_THS7360_SF_HD_MODE;
                    break;

                default:
                case FVID2_STD_1080P_60:
                case FVID2_STD_1080P_50:
    Vps_printf ( " KAILASH %s:%d\n",__FUNCTION__, __LINE__ );
                    thsCtrl = SYSTEM_THS7360_SF_TRUE_HD_MODE;
                    break;
            }
            System_ths7360SetSfParams(thsCtrl);
            System_ths7360SetSdParams(SYSTEM_THSFILTER_ENABLE_MODULE);
    #endif
    #endif // #ifndef IPNC
        }

    #if defined(TI_8107_BUILD)
        Vps_rprintf("HDCOMPCLK\n");
        retVal = System_platformSelectHdCompClkSrc(SYSTEM_VPLL_OUTPUT_VENC_A);
        UTILS_assert(retVal == FVID2_SOK);
    #endif

    #ifdef TI816X_DVR
        retVal = System_platformSelectHdCompSyncSrc(SYSTEM_HDCOMP_SYNC_SRC_DVO1, 1);
        UTILS_assert(retVal == FVID2_SOK);
    #endif
        retVal = FVID2_control(
                     gSystem_objVpss.fvidDisplayCtrl,
                     IOCTL_VPS_DCTRL_SET_CONFIG,
                     &gSystem_objVpss.displayCtrlCfg,
                     NULL);
        //GT_assert( GT_DEFAULT_MASK, retVal==FVID2_SOK);
        UTILS_assert(retVal == FVID2_SOK);

        if (gSystem_objVpss.enableConfigExtVideoEncoder)
        {
    #ifndef _IPNC_HW_PLATFORM_
    #ifdef SYSTEM_USE_VIDEO_DECODER
    #ifndef TI8107_DVR
           if((pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].resolution == VSYS_STD_1080P_60) ||
               (pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].resolution == VSYS_STD_720P_60)) {
                System_hdmiStart(pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].resolution, System_getBoardId());
            }
    #endif
    #endif
    #endif // #ifndef IPNC
        }

    Vps_printf ( " KAILASH %s:%d\n",__FUNCTION__, __LINE__ );
        return retVal;
    }

    thanks

    Kailash

  • 0 in reply to Kailash Negi
    TI__Guru**** 398890 points
    Hi Kailash,

    But do you any black background color on the display? Does your display detect input stream?

    Rgds,
    Brijesh
  • 0 in reply to Brijesh Jadav
    Intellectual 590 points
    Hi Brijesh,

    No display is Black and its showing Input Not supported.

    Thanks
    Kailasg
  • 0 in reply to Kailash Negi
    TI__Guru**** 398890 points
    Does your TV support 1080p resolution on VGA?

    Regards,
    Brijesh
  • 0 in reply to Brijesh Jadav
    Intellectual 590 points

    Hi Brijesh,

    thanks , i ve changed the display it is working now, But now i am facing problem with paths.

    i want to run HDMI and HDDAC on different paths, Is this tree correct

    Vps_DcConfig gSystem_dctrlTriDisplayConfig = {
        VPS_DC_USERSETTINGS,                                   /* Use Case */
        /* Edge information */
        {
            {VPS_DC_BP0_INPUT_PATH, VPS_DC_VCOMP_MUX},
            {VPS_DC_VCOMP_MUX, VPS_DC_VCOMP},
            {VPS_DC_CIG_NON_CONSTRAINED_OUTPUT, VPS_DC_HDMI_BLEND},
            //{VPS_DC_CIG_NON_CONSTRAINED_OUTPUT, VPS_DC_HDCOMP_BLEND},
              {VPS_DC_BP1_INPUT_PATH, VPS_DC_HDCOMP_MUX},
              {VPS_DC_HDCOMP_MUX, VPS_DC_CIG_PIP_INPUT},
              //{VPS_DC_CIG_PIP_OUTPUT, VPS_DC_DVO2_BLEND},
              {VPS_DC_CIG_PIP_OUTPUT, VPS_DC_HDCOMP_BLEND},
            {VPS_DC_SEC1_INPUT_PATH, VPS_DC_SDVENC_MUX},
            {VPS_DC_SDVENC_MUX, VPS_DC_SDVENC_BLEND},
            {VPS_DC_GRPX0_INPUT_PATH, VPS_DC_HDMI_BLEND},
            {VPS_DC_GRPX1_INPUT_PATH, VPS_DC_HDCOMP_BLEND},
              //{VPS_DC_GRPX1_INPUT_PATH, VPS_DC_DVO2_BLEND},
            {VPS_DC_GRPX2_INPUT_PATH, VPS_DC_SDVENC_BLEND},

            {VPS_DC_MAIN_INPUT_PATH, VPS_DC_VCOMP},
            {VPS_DC_AUX_INPUT_PATH, VPS_DC_VCOMP_MUX},
            //{VPS_DC_BP1_INPUT_PATH, VPS_DC_SDVENC_MUX},
        },

        14,
        /* VENC information */
        {
         /* Mode information */
         {
          {VPS_DC_VENC_HDMI, {FVID2_STD_1080P_60}
           }
          ,                                                    /* 1080p30 is mode
                                                                * is overwritten
                                                                * later inside
                                                                * System_displayCtrlInit
                                                                */
          {VPS_DC_VENC_HDCOMP, {FVID2_STD_1080P_60}
          },                                                   /* 1080p30 is mode
                                                                * is overwritten
                                                                * later inside
                                                                * System_displayCtrlInit
                                                                */
          //{VPS_DC_VENC_DVO2, {FVID2_STD_1080P_60}},
          {VPS_DC_VENC_SD, {FVID2_STD_NTSC}
           }
          }
         ,
         (VPS_DC_VENC_HDMI | VPS_DC_VENC_HDCOMP),                /* Tied VENC bit
                                                                * mask */
         3u                                                    /* Number of VENCs
                                                                */
         }
    };

    thanks

    Kailash

  • 0 in reply to Kailash Negi
    TI__Guru**** 398890 points

    Hi Kailash,

    Two Problems.

    Do you want to tie both HDMI and HDCOMP. I guess you want to run different resolutions on both the display and treat them independent. In that case, set the tied VENC bit to 0.

    The number of edges are set to 14. But actually there are 13 edges in the tree. 

    Other than this, it looks ok.

    Rgds,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Intellectual 590 points
    Hi Brijesh,

    I tried with your suggestion, But display controller init is failing to set IOCTL_VPS_DCTRL_SET_CONFIG , The code where it is actually failing while setting DCTRL_SET_CONFIG
    if ((VPS_DC_VENC_HDCOMP == vencInfo->modeInfo[cnt].vencId) &&
    ((0u == vencInfo->tiedVencs) || (vencInfo->numVencs < 2u)))
    {
    Vps_printf ( " KAILASH common %s:%d\n",__FUNCTION__, __LINE__ );
    retVal = FVID2_EINVALID_PARAMS;
    break;
    }

    Apart from this. In the code i can see if the tied encoder bit is is 0 then setting of clock for VENC_HDCOMP is not been done, following is the code.

    if(!(dctrlTriDisplayConfig->vencInfo.tiedVencs)) {
    Vps_rprintf("IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC ###################\n");
    /* Set the Clock source for off-chip HDMI */
    clkSrc.venc = VPS_DC_VENC_DVO2;
    clkSrc.clkSrc = VPS_DC_CLKSRC_VENCA;
    // clkSrc is the same as DVO2 for this App
    retVal = FVID2_control(
    gSystem_objVpss.fvidDisplayCtrl,
    IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC,
    &clkSrc,
    NULL);
    //GT_assert( GT_DEFAULT_MASK, retVal==FVID2_SOK);
    UTILS_assert(retVal == FVID2_SOK);

    /* Set the Clock source for on-chip HDMI */
    clkSrc.venc = VPS_DC_VENC_HDMI;
    clkSrc.clkSrc = VPS_DC_CLKSRC_VENCD;
    retVal = FVID2_control(
    gSystem_objVpss.fvidDisplayCtrl,
    IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC,
    &clkSrc,
    NULL);
    //GT_assert(GT_DEFAULT_MASK, retVal == FVID2_SOK);
    UTILS_assert(retVal == FVID2_SOK);

    }

    thanks
    Kailash
  • 0 in reply to Kailash Negi
    TI__Guru**** 398890 points
    Hi Kailash,

    sorry, on DM388, HDCOMP has to be tied with one of HDMI or DVO2. I just recollect this info.
    HDCOMP cannot work independently. You have to tie it with another VENC.
    If you want to HDMI and HDCOMP to be independent, tie HDCOMP with DVO2 and set the same mode as HDCOMP in DVO2 also. That should work.

    Rgds,
    Brijesh
  • 0 in reply to Brijesh Jadav
    Intellectual 590 points
    Hi Brijesh,

    My requirement is set HDMI, HDDAC, and DVO2 independently on different paths. Is this achievable in DM388.
    HDMI will support 1080p and
    HDDAC NTSC/PAL
    and
    DVO2 720p and 1080p.

    If this is achievable then how to do that?

    Thanks
    Kailash
  • 0 in reply to Kailash Negi
    TI__Guru**** 398890 points
    Hi Kailash,

    why do you require NTSC/PAL on HDDAC output?
    You could use SD DAC for getting NTSC/PAL.

    Rgds,
    Brijesh
  • 0 in reply to Brijesh Jadav
    Intellectual 590 points
    HI Brijesh,

    Supporting NTSC/Pal on HDDAC is requirement on our custom (dm388)board.

    In The Eval board i want to support HDMI 1080P, HDDAC 720p/1080p, DVO2 1080p/720p.
    Is it possible to create these three encoders independently , tie up on three different paths , so that my app will be capture and tridisplay (HDMI(1080p),DVO2(720p),HDDAC(720P) on different path ie three display links. Please Clear this doubt.

    Thanks
    Kailash
  • 0 in reply to Kailash Negi
    TI__Guru**** 398890 points
    Hi Kailash,

    HDDAC cannot run independently, it has to be running in synchronous with either HDMI or DVO2.
    Having said that, you could have HDMI and HDCOMP both tied and running 1080p mode and two different paths connected to both of these VENCs.
    When you want to get 720p output, you have to tie HDCOMP with DVO2 and then you could have two different paths connected to these path.
    So connecting two or three independent paths is not a problem. There are four Video pipeline available in HDVPSS and you could connect to any of the VENC. provided that these paths are not being used in mem2mem mode.
    But the problem is, HDCOMP has to run in synchronous with the one of the other VENC.

    Regards,
    Brijesh
  • 0 in reply to Brijesh Jadav
    Intellectual 590 points
    HI Brijesh,

    Based on the discussion understanding of the code are these Conclusions are correct.
    1. Paths can be either BP0, BP1, SC2 can either be connected to VCOMP_MUX and HDCOMP_MUX.
    2. SC1 can be connected to VCOMP .
    3.SEC1 is connected to SDVENC_MUX.
    4. The combinations of path Can be
    {VPS_DC_VCOMP_MUX, VPS_DC_VCOMP},
    and
    {VPS_DC_HDCOMP_MUX, VPS_DC_CIG_PIP_INPUT}
    and
    {VPS_DC_SEC1_INPUT_PATH, VPS_DC_SDVENC_MUX},
    {VPS_DC_SDVENC_MUX, VPS_DC_SDVENC_BLEND}.
    5. So according to above combinations we can have maximum three Paths and two of them can either Point to
    { {HDMI,HDCOMP}, DVO2} or {HDMI, {HDCOMP,DVO2}}.
    6. We can use only the following combination
    { {HDMI,HDCOMP}, DVO2} or {HDMI, {HDCOMP,DVO2}}.
    and
    {HDMI, DVO2, HDCOMP} is not possible.
    7. SEC1 always points to SDCOMP_BLEND so it can be used as third path always.

    Tryout:
    I have tried to Change the path HDCOMP to BP1 when (HDMI and HDCOMP) are tied up but its failing to during link start.

    thanks
    Kailash
  • 0 in reply to Kailash Negi
    Intellectual 590 points
    Hi Brijesh,

    Simplification of the questions asked in the last post.
    If BP0 is pointing to VCOMP_MUX .
    1. If BP1 and SC2 paths are also pointing to VCOMP_MUX . Then We cannot start BP0/BP1/SC2 simultaneously ,only one can be used at one time.
    2 SEC1 can work independently as it always points to SDVENC_MUX.

    If BP0 is pointing to HDCOMP_MUX .
    1. If BP1 and SC2 paths are also pointing to HDCOMP_MUX . Then We cannot start BP0/BP1/SC2 simultaneously only one can be used at one
    time.
    2 SEC1 can work independently as it always points to SDVENC_MUX.

    If the Above statements are true then, We Can use only the one of the following Three Path Pairs Simultaneously.
    1. BP0 on VCOMP_MUX, BP1 on HDCOMP_MUX, SEC1 on SDVEDENC_MUX.
    2. BP1 on VCOMP_MUX, BP0 on HDCOMP_MUX, SEC1 on SDVEDENC_MUX.
    3. SC2 on VCOMP_MUX, BP0 on HDCOMP_MUX, SEC1 on SDVEDENC_MUX.
    4. SC2 on VCOMP_MUX, BP1 on HDCOMP_MUX, SEC1 on SDVEDENC_MUX.
    5. BP0 on VCOMP_MUX, SC2 on HDCOMP_MUX, SEC1 on SDVEDENC_MUX.
    6. BP1 on VCOMP_MUX, SC2 on HDCOMP_MUX, SEC1 on SDVEDENC_MUX.
    4. SC1 on VCOMP, BP0/BP1/SC2 on HDCOMP_MUX, SEC1 on SDVEDENC_MUX.


    I have started a new thread for tridisplay.

    e2e.ti.com/.../630708

    Thanks
    Kailash
  • 0 in reply to Kailash Negi
    TI__Guru**** 398890 points
    Hi Kailash,

    VCOMP_MUX and HDCOMP_MUX, as the name suggest, are actually muxes, so they allow only one input path active at any point of time.
    Ths mean, you could have two independent video pipeline going to the VENC, one through VCOMP_MUX and other through HDCOMP_MUX. We cannot use third video pipeline. But we can use GRPX pipelines and connect to one of the VENC.

    Rgds,
    Brijesh
  • 0 in reply to Brijesh Jadav
    Intellectual 590 points
    Hi Brijesh,

    Thanks for clarification.

    While creating Display link one of the parameter is display Id for ex "DISPLAY_LINK_DISPLAY_SC2",
    Is it possible to provide GPRX 0/1/2 path there?

    Thanks
    Kailash
  • 0 in reply to Kailash Negi
    TI__Guru**** 398890 points

    Hi Kailash,

    If i remember correctly, display link do not support GRPX. There is a separate link for the GRPX.

    Please use GRPX link for the GRPX path.

    Regards,

    Brijesh 

  • 0 in reply to Brijesh Jadav
    Intellectual 590 points
    Hi Brijesh,

    I am not able to locate GPRX link in ipnc3.8.1 source code. Can you please Point Where to find it?

    Thanks
    Kailash
  • 0 in reply to Kailash Negi
    Intellectual 590 points
    Hi Brijesh,

    In the MCFW framework of ipnc 3.8.1 there is no support for GPRX link.

    Thanks
    Kailash
  • 0 in reply to Kailash Negi
    Intellectual 590 points
    Hi Brijesh,

    I have implemented GPRX link inside MCFW framework, Taking gprx link in the HDVPSS example code as reference.

    I have connected HDCOMP to GPRX1 and trying to create the GPRX link but the application is hanged during create of GPRX link.I have checked the code with some debug prints , Code is calling GRPXDrvCreate() but it is not coming out of FVID2_create. No errors only the app is hanged. What could be the problem?

    Gprx link is supported in 3.8.1 MCFW framework?


    Thanks
    Kailash
  • 0 in reply to Kailash Negi
    Intellectual 590 points
    Hi Brijesh,

    We want to support NTSC / Pal on HDDAC on our custom board . Does HDDAC(HDCOMP_VENC) supports NTSC/PAL?

    thanks
    Kailash
  • 0 in reply to Kailash Negi
    TI__Guru**** 398890 points

    Hi Kailash,

    Let me check, GRPX link is supported. But i dont remember where it is.  Might be somewhere in the example/utils folder.

    Regards,

    Brijesh

  • 0 in reply to Kailash Negi
    TI__Guru**** 398890 points
    Hi Kailash,

    If i remember correctly, it can support 480i/576i, but not exactly NTSC/PAL. Please go through the TRM to figure out.
    Btw, why dont you use SD DAC for NTSC/PAL output?

    Rgds,
    Brijesh
  • 0 in reply to Brijesh Jadav
    Intellectual 590 points
    Hi brijesh,

    I ve checked with 480i its working.
    We want to use hddac because, sddac in dm388evm only supports composite video, s-video is not supported.

    In our implementation an external ntsc/pal encoder is connected to hddac component out. The external encoder supports s- video.

    One more fact here is, if I tie up dvo2 and hdcomp and I am commenting out path to dvo2 blend and taking only hdcomp blend path in DC mesh then the display connected to hdcomp does not show stable video (flickering).
    But when i uncomment hdcomp blend path, the display is showing correctly on hdcomp.
    Is this because hdcomp can run only synchronous to tied venc?

    What is TRM?

    Thanks
    Kailash