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SD card reading problem on DM3730

Vivian Sun
Prodigy 70 points
Other Parts Discussed in Thread: DM3730, TPS65951

Hi,

    Our costomer is developing DM3730, using Android_Linux_Kernel_2_6_32 in TI_Android_Froyo_DevKit-V2.2.

When reading a big file(about 100MB) from the sdcard, they found some bytes(less than 10bytes) error with bit-flip.

Testing procedure:

1. read a small file(less than 1MB) from sdcard ----  Pass

 2. write a small file to sdcard  ---- Pass

 3. write a big file to sdcard ---- Pass

 4. read a big file from sdcard ---- Failed

   the failed output as follows:

#cmp -lb file1 file2

33325828 275 M-=  277 M-?

67805956 320 M-P  321 M-Q

   However, the HSMMC read out all data without reporting any error in reg[OMAP_HSMMC_STAT].

   Reading sdcard in some boards is ok no matter how large the file size is,  but this issue happens on most of boards.

 

 This product is in Pilot run,  and will use SD card for system update. So it's very important and urgent.

Please help. 

 

Vivian

  • 0
    Guru 31670 points

    Vivian,

    You can try the following.

    1. Confirm whether the issue is occurring with a particular vendor's card or not.

    2. Reduce the clock speed of the mmc, basically from 48MHz to 24MHz or less and see whether the issue occurs or not

    3. Change the bus width from 4-bit to 1-bit and try whether the issue is reproducible.

    -Renjith

    www.pathpartnertech.com

  • 0 in reply to Renjith Thomas
    Prodigy 145 points

    Hi,

    I am experiencing the same problem. The phenomena occurs on uSD cards from different vendors. I haven't tried slowing down or narrowing SD bus till now. SD standard states all data packets has CRC, so in case of data error, the controller should easily detect and report it. Are there any additional known HSMMC core limitations, not described within official errata document?


    The system consists of DM3730 w/ TPS65951 companion chip. Memory - Micron LPDDR DDR333MHz (-6 timing rate). External oscillator - 38,4MHz (according to EHCI clocking advise presented in errata document). Core clock PLL coefficients - m=312, n=36 (332,8MHz).

    Paul