Custom Camera Driver

Hi Alex,

The improvement of the performance of the camera could be reached by optimizing of the driver. I now that it sounds very general but I have not information about software and OS. I recommend you to check the frequency of the processor is it set at the maximum.

BR

Tsvetolin Shulev

Thanks for your response. I am running Angstrom Linux, and the frequency is running at 1 GHz. I am getting a readout of about 3.2 MHz from the kernel module after everything is said and done. Is there any way to increase this?

Thanks,

    Alex Busman

The frequency of the processor - 1 GHz is correct but I'm not sure that understood what frequency is 3.2 MHz. Could you tell me what is the framerate which you have now and what about the resolution?

BR

Tsvetolin Shulev

I am trying to capture an image that is 14.4 MPixels, and it is currently taking about 4.5 seconds to acquire one frame or 3.2 MPixels/sec. The way I do it, is I read the CAM_D pins as a bank, store it in memory, and then I manually clock the camera to acquire the data. Basically, I toggle a pin low, read the data pins, and then toggle it back high and repeat for all 14.4 MPixels. I'm not using HS or VS or any sort of framing, I'm just trying to clock in 12-bit parallel data using GPIO. I would, however, love to use the camera ISP built in to the processor, but I do not understand how to use it or interface with it.

Now I understand what exactly do you do. The speed of data transfer in your environment depends on the CCD sensor which comes to the processor via cam_pclk. You should check documentation of your camera sensor whether it supports higher frequency. In general case the camera sensor gets clock via cam_xclka or cam_xclkb but in your schematic I'm not sure how it is connected. Then the frequency of data transfer should be adjusted by sensor PLL.

BR

Tsvetolin Shulev

Thanks for the response. So if I am to understand this correctly, the sensor receives a pulse from XCLKA or XCLKB, and then readies pixel data on the data lines, and pulls the PCLK high/low to verify it has valid data, and then the DaVinci sees the PCLK pulse and reads from the data pins right into memory, and then the DaVinci sends another pulse over the XCLKs and the process repeats. Is this capability available in the OMAP3 V4L2 camera driver supplied in the kernel, and does it only support this protocol? The reason I ask, is because I am designing the camera to conform with the DaVinci's protocol, and I want a complete understanding of what I have to implement on the camera's FPGA.

Thank you for all your help,

    Alex Busman