DM3730: L1 and L2 cache interleaving

In further discussion offline on this, the question applies to all internal memories for both the ARM Cortex-A8 and C64x+ DSP cores.

For neutron upsets mitigation, interleaving of physical location of memory cells would be effective. What [De Yao is] looking for is if there is any interleaving scheme implemented on the L1 and L2 cache memories. For example, adjacent data bits in one address interleaved with data bits from a different address, physically. The idea is to minimize the chance of multiple bits in one memory address being altered by one hit of a high energy particle.

This request is effectively to report on the internal design architecture of all of these memories and to state whether any physical interleaving is done so that bits of an individually addressed byte are separated by the bits of another individually addressed byte, hopefully from a separate 32-bit word.

Regards,
RandyP