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Hi Zeroman,

Can you provide the error details and software version details? From where you are writing?

Check whether the ISS clock is enabled or not, if not then enable the clock first, then you can able to access the address space.

Regards

AnilKumar

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Hi, Anil

The reason may be that the clock is not turned on.But I do not know where to open iss the clock.

I can not find the the iss clock register.
Thank you very much.

Hi Zeroman,

You can look at section "2.9.9 CM_ISP Registers" in TRM and (arch/arm/mach-omap2/cm81xx.h) 

Regards

AilKumar

Please mark this Forum post as answered via the Verify Answer button below if it helps answer your question.  Thanks!

Hi, Anil,

I added the code in front of the iss initialization，

Int32 Iss_init(Ptr arg)
{
    Int32 retVal = 0;

#define PRCM_BASE            0x48180000
#define TI814X_CM_ISP_MOD            0x0700  /* 256B */

    /* CM_ISP */
#define TI814X_CM_ISP_CLKSTCTRL            (PRCM_BASE + TI814X_CM_ISP_MOD + 0x0000)
#define TI814X_CM_ISP_ISP_CLKCTRL        (PRCM_BASE + TI814X_CM_ISP_MOD + 0x0020)
#define TI814X_CM_ISP_FDIF_CLKCTRL        (PRCM_BASE + TI814X_CM_ISP_MOD + 0x0024)
    *(unsigned int *) TI814X_CM_ISP_CLKSTCTRL = 0x2;
    *(unsigned int *) TI814X_CM_ISP_ISP_CLKCTRL    = 0x2;
    *(unsigned int *) TI814X_CM_ISP_FDIF_CLKCTRL = 0x2;

    if (0 != retVal)
    {
        Vps_printf("%s: Error @ line %d\n", __FUNCTION__, __LINE__);
        return (retVal);
    }

    if (0 == retVal)
    {
           retVal = issCommonInit();
    }

......

static Int32 issCommonInit(void)
{
    Int32 retVal = 0;
    Bool simcopInit = FALSE;
    
#ifdef POWER_OPT_DSS_OFF
    simcopInit = FALSE;
#else
   simcopInit = TRUE;
#endif

   
    CSL_SimcopRegsOvly pSimcopRegs =   (CSL_SimcopRegsOvly) CSL_SIMCOP_BASE_ADDRESS;
    CSL_FINS(pSimcopRegs->CLKCTRL, SIMCOP_CLKCTRL_DMA_CLK,   CSL_SIMCOP_CLKCTRL_DMA_CLK_SUBMODULE_ENABLE_REQ);
    (unsigned int *) 0x52000010 = 0x023;        //Soft-reset ISS IP and make auto-standby=TRUE ;

The implementation of any one of these three code will crash.As if the clock is still not open.

    CSL_SimcopRegsOvly pSimcopRegs =   (CSL_SimcopRegsOvly) CSL_SIMCOP_BASE_ADDRESS;
    CSL_FINS(pSimcopRegs->CLKCTRL, SIMCOP_CLKCTRL_DMA_CLK,   CSL_SIMCOP_CLKCTRL_DMA_CLK_SUBMODULE_ENABLE_REQ);
    (unsigned int *) 0x52000010 = 0x023;        //Soft-reset ISS IP and make auto-standby=TRUE

Thank you.

Hello Zeroman,

If you are using the DM8127 with ipnc_rdk software, I think the reason you may be getting a crash is because you may be trying to access ISS from the wrong base address. The M3 can access ISS through a internal interconnect bus and via the MMU. This the MMU address mapping also is important.

In the default software configuration the ISS base addresses can be refered in the following file:

ti\psp\iss\hal\cred_cram\cred\src\cortexm3_sys_ape\cred.c

The base address should be 0x55040010 instead of 0x52000010.

Please confirm if this works.

Regards

Rajat

Hello Rajat,

  In TMS320DM814x Imaging Subsystem(ISS) Technical Reference Manual.pdf(Literature Number: SPRUGZ8 June 2011),

ISS base addr is 0x52010000.

Your  is 0x52000010.

I tried two kinds of methods, but are invalid.

I modified the code as follows:

--- a/ti_tools/iss/iss_02_00_00_00/packages/ti/psp/iss/hal/cred_cram/cred/src/cortexm3_sys_ape/cred.c
+++ b/ti_tools/iss/iss_02_00_00_00/packages/ti/psp/iss/hal/cred_cram/cred/src/cortexm3_sys_ape/cred.c
@@ -1086,7 +1086,7 @@ const REG_UWORD32 CRED_instPhysAddr[CRED_NUM_INSTANCES] = {
     0x54164000,
     0x54165000,
     0x54200000,
-    0x55040000,
+    0x52010000,
     0x55040400,
     0x55041000,
     0x55041170,
@@ -2034,7 +2034,7 @@ const CRED_instances_t CRED_instances[CRED_NUM_INSTANCES] = {
     {&CRED_instVirtAddr[333], 0x54164000, 4096, "I_CSTF1"},
     {&CRED_instVirtAddr[334], 0x54165000, 4096, "I_CSTF2"},
     {&CRED_instVirtAddr[335], 0x54200000, 120, "RT0"},
-    {&CRED_instVirtAddr[336], 0x55040000, 144, "ISS_REGS"},
+    {&CRED_instVirtAddr[336], 0x52010000, 144, "ISS_REGS"},
     {&CRED_instVirtAddr[337], 0x55040400, 60, "TCTRL"},
     {&CRED_instVirtAddr[338], 0x55041000, 368,
      "CSI2_RECEIVER_A__CSI2_RECEIVER_REGS1"},

I can not do anything, I hope you give suggestions, thank you very much.

Hi Zeroman, 

Can you confirm if you are able to access iss registers @ 0x55040000 ?

Do you want to access ISS registers from M3 process or A8 processor?

Regards

Rajat

Based on this thread I succeeded with following code: 

*((unsigned int*)0x48180d00) = 0x2;
*((unsigned int*)0x48180d10) = 0x3;
*((unsigned int*)0x48180700) = 0x2;
*((unsigned int*)0x48180720) = 0x2;
*((unsigned int*)0x48180724) = 0x2;

// had to add first two lines in order to access following register at all:

*((unsigned int*)0x55050010) = 0x23; // ISP5_SYSCONFIG

// ISP5_SYSCONFIG had been readable until write so that following further steps are required:

*((unsigned int*)0x55040080) = 0xFFFF0000; // ISS_CTRL
*((unsigned int*)0x55040084) = 0xF0000002;  // ISS_CLKCTRL

 // at this point it seems that ISS registers are fully accessible from the M3

 How should I reconfigure the MMU mapping table to access these registers (from 0x55040000 base address) on Cortex A8 host as well?

Krisztian,

M3 accesses go via MMU, but for A8 the accesses don't go via the MMU. If you want to access ISS registers via A8 or on Linux, you could directly mmap the physical to virtual address and access the registers.

Regards

Rajat

Thanks, Rajat! 

It seems that I cannot verify your answer. I should have started a new thread. :-\

From the A8, I kept trying with 0x55050010. Or is that address to be changed without the MMU?

fd = open("/dev/mem", O_RDWR | O_SYNC);

page_addr = (unsigned char *) mmap( 0, getpagesize(), PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0x5505000 );

offset = (unsigned int *)(page_addr + 0x10);

// I get  no errors until here.

printf("%x\n",*offset);

// Here a bus error comes.

Linux is configured almost as in IPNC DM8148 RDK except for the vpss notify area. It is missing from bootargs in order to run msgQ sample.

Regards, 

Krisztián

PS: I am continuing thread here: http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/213095.aspx!