How does the edma_pins works. Description is missing in the present docs.
Our SW guy has found registers to select edma_evt in the TI linux source for each Dma channel, which is not documented either.
We need to know if the edma_evt* are edge triggered or level triggered etc.
Is there additional registers to set them up?
The source of edma_evt* pins will be a FPGA. One DMA channel for each pin.
We bill our own GNU linux 2.6 kernel plus TI drivers for the evm kit
Please provide register full register documentation or at less full doc on the edma_evt* pins.?
I
Hi Peter,
Can you give us those registers to select edma_evt so we can trace it with the SW team and fix the doc?
Thanks,
Viet
Viet,
I will send you via email an older draft doc describing the EVTMUX register, that probably should have been in the TRM by now. Please see if this info can be made public here at E2E or in the TRM.
However, the remaining *questions* to be answered are:
-Are the EDMA_EVT0..3 pins level or edge trigged?
-What polarity is used?
-Can the polarity be re-programmed to opposite, and if so, what configuration register should be used then?
Thanks for investing further.
/Magnus
For the EDMA external events, these are active HIGH and cannot be configured. They can be anything equal to or greater than 3P, P being period of the EDMA clock (which is the same as the L3 clock period).
BR,
Some more inputs:
For the EDMA external events, these are active HIGH and cannot be configured, a transition from inactive (low) to active (high) will set the Event Register (ER). They can be anything equal to or greater than 3P, P being period of the EDMA clock (which is the same as the L3 clock period).
EDMA_EVT0_MUX0 (edma_evt0 on mux0) is configured in PINCNTL133 register, EDMA_EVT0_MUX1 (edma_evt0 on mux1) is configured in PINCNTL116.
EDMA_EVT1_MUX0 (edma_evt1 on mux0) is configured in PINCNTL132 register, EDMA_EVT1_MUX1 (edma_evt1 on mux1) is configured in PINCNTL80.
EDMA_EVT2_MUX0 (edma_evt2 on mux0) is configured in PINCNTL131 register, EDMA_EVT2_MUX1 (edma_evt2 on mux1) is configured in PINCNTL16.
EDMA_EVT3_MUX0 (edma_evt3 on mux0) is configured in PINCNTL127 register, EDMA_EVT3_MUX1 (edma_evt3 on mux1) is configured in PINCNTL15.
There is also TPCC's EVT_MUX_[#evt_number] register (in Control Module), which map different DMA event source to TPCC event number:
0x1C (28) - select EDMA_EVT0 Pin0x1D (29) - select EDMA_EVT1 Pin
0x1E (30) - select EDMA_EVT2 Pin
0x1F (31) - select EDMA_EVT3 Pin
Hi
Thanks, We found out on our own quit a wile ago, but I have been able to log in here, some browser stuff
/Peter